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[Qemu-devel] [PATCH RFC qom-cpu 35/41] cpu: Introduce CPUClass::memory_r
From: |
Andreas Färber |
Subject: |
[Qemu-devel] [PATCH RFC qom-cpu 35/41] cpu: Introduce CPUClass::memory_rw_debug() for target_memory_rw_debug() |
Date: |
Sat, 29 Jun 2013 22:01:51 +0200 |
Make inline target_memory_rw_debug() always available and change its
argument to CPUState. Let it check if CPUClass::memory_rw_debug provides
a specialized callback and fall back to cpu_memory_rw_debug() otherwise.
The only overriding implementation is for 32-bit sparc.
This prepares for changing GDBState::g_cpu to CPUState.
Signed-off-by: Andreas Färber <address@hidden>
---
gdbstub.c | 21 ++++++++++++---------
include/qom/cpu.h | 2 ++
target-sparc/cpu.c | 3 +++
target-sparc/cpu.h | 5 ++---
target-sparc/mmu_helper.c | 8 +++++---
5 files changed, 24 insertions(+), 15 deletions(-)
diff --git a/gdbstub.c b/gdbstub.c
index 43ecc0d..fa44550 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -42,15 +42,16 @@
#include "sysemu/kvm.h"
#include "qemu/bitops.h"
-#ifndef TARGET_CPU_MEMORY_RW_DEBUG
-static inline int target_memory_rw_debug(CPUArchState *env, target_ulong addr,
- uint8_t *buf, int len, int is_write)
+static inline int target_memory_rw_debug(CPUState *cpu, target_ulong addr,
+ uint8_t *buf, int len, bool is_write)
{
- return cpu_memory_rw_debug(ENV_GET_CPU(env), addr, buf, len, is_write);
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+
+ if (cc->memory_rw_debug) {
+ return cc->memory_rw_debug(cpu, addr, buf, len, is_write);
+ }
+ return cpu_memory_rw_debug(cpu, addr, buf, len, is_write);
}
-#else
-/* target_memory_rw_debug() defined in cpu.h */
-#endif
enum {
GDB_SIGNAL_0 = 0,
@@ -2240,7 +2241,8 @@ static int gdb_handle_packet(GDBState *s, const char
*line_buf)
if (*p == ',')
p++;
len = strtoull(p, NULL, 16);
- if (target_memory_rw_debug(s->g_cpu, addr, mem_buf, len, 0) != 0) {
+ if (target_memory_rw_debug(ENV_GET_CPU(s->g_cpu), addr, mem_buf, len,
+ false) != 0) {
put_packet (s, "E14");
} else {
memtohex(buf, mem_buf, len);
@@ -2255,7 +2257,8 @@ static int gdb_handle_packet(GDBState *s, const char
*line_buf)
if (*p == ':')
p++;
hextomem(mem_buf, p, len);
- if (target_memory_rw_debug(s->g_cpu, addr, mem_buf, len, 1) != 0) {
+ if (target_memory_rw_debug(ENV_GET_CPU(s->g_cpu), addr, mem_buf, len,
+ true) != 0) {
put_packet(s, "E14");
} else {
put_packet(s, "OK");
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index 9717650..820dca4 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -77,6 +77,8 @@ typedef struct CPUClass {
int reset_dump_flags;
void (*do_interrupt)(CPUState *cpu);
CPUUnassignedAccess do_unassigned_access;
+ int (*memory_rw_debug)(CPUState *cpu, uint64_t addr,
+ uint8_t *buf, int len, bool is_write);
void (*dump_state)(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
int flags);
void (*dump_statistics)(CPUState *cpu, FILE *f,
diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c
index c3e2d3d..bd9d216 100644
--- a/target-sparc/cpu.c
+++ b/target-sparc/cpu.c
@@ -782,6 +782,9 @@ static void sparc_cpu_class_init(ObjectClass *oc, void
*data)
cc->do_interrupt = sparc_cpu_do_interrupt;
cc->dump_state = sparc_cpu_dump_state;
+#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
+ cc->memory_rw_debug = sparc_cpu_memory_rw_debug;
+#endif
cc->set_pc = sparc_cpu_set_pc;
cc->synchronize_from_tb = sparc_cpu_synchronize_from_tb;
#ifndef CONFIG_USER_ONLY
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index 0f35a22..b043772 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -526,9 +526,8 @@ target_ulong mmu_probe(CPUSPARCState *env, target_ulong
address, int mmulev);
void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUSPARCState *env);
#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
-int target_memory_rw_debug(CPUSPARCState *env, target_ulong addr,
- uint8_t *buf, int len, int is_write);
-#define TARGET_CPU_MEMORY_RW_DEBUG
+int sparc_cpu_memory_rw_debug(CPUState *cpu, uint64_t addr,
+ uint8_t *buf, int len, bool is_write);
#endif
diff --git a/target-sparc/mmu_helper.c b/target-sparc/mmu_helper.c
index bf89236..66ed1ba 100644
--- a/target-sparc/mmu_helper.c
+++ b/target-sparc/mmu_helper.c
@@ -353,10 +353,12 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf,
CPUSPARCState *env)
* reads (and only reads) in stack frames as if windows were flushed. We assume
* that the sparc ABI is followed.
*/
-int target_memory_rw_debug(CPUSPARCState *env, target_ulong addr,
- uint8_t *buf, int len, int is_write)
+int sparc_cpu_memory_rw_debug(CPUState *cs, uint64_t address,
+ uint8_t *buf, int len, bool is_write)
{
- CPUState *cs = CPU(sparc_env_get_cpu(env));
+ SPARCCPU *cpu = SPARC_CPU(cs);
+ CPUSPARCState *env = &cpu->env;
+ target_ulong addr = address;
int i;
int len1;
int cwp = env->cwp;
--
1.8.1.4
- [Qemu-devel] [PATCH RFC qom-cpu 23/41] target-xtensa: Change gen_intermediate_code_internal() arg to XtensaCPU, (continued)
- [Qemu-devel] [PATCH RFC qom-cpu 23/41] target-xtensa: Change gen_intermediate_code_internal() arg to XtensaCPU, Andreas Färber, 2013/06/29
- [Qemu-devel] [PATCH RFC qom-cpu 24/41] target-alpha: Change DisasContext::env to CPUState, Andreas Färber, 2013/06/29
- [Qemu-devel] [PATCH RFC qom-cpu 26/41] gdbstub: Update gdb_handlesig() and gdb_signalled() Coding Style, Andreas Färber, 2013/06/29
- [Qemu-devel] [PATCH RFC qom-cpu 29/41] gdbstub: Change syscall callback argument to CPUState, Andreas Färber, 2013/06/29
- [Qemu-devel] [PATCH RFC qom-cpu 27/41] cpu: Change cpu_single_step() argument to CPUState, Andreas Färber, 2013/06/29
- [Qemu-devel] [PATCH RFC qom-cpu 28/41] kvm: Change kvm_{insert, remove}_breakpoint() argument to CPUState, Andreas Färber, 2013/06/29
- [Qemu-devel] [PATCH RFC qom-cpu 25/41] cpu: Move singlestep_enabled field from CPU_COMMON to CPUState, Andreas Färber, 2013/06/29
- [Qemu-devel] [PATCH RFC qom-cpu 30/41] gdbstub: Change gdb_handlesig() argument to CPUState, Andreas Färber, 2013/06/29
- [Qemu-devel] [PATCH RFC qom-cpu 32/41] gdbstub: Change gdb_{read, write}_register() argument to CPUState, Andreas Färber, 2013/06/29
- [Qemu-devel] [PATCH RFC qom-cpu 31/41] gdbstub: Change GDBState::c_cpu to CPUState, Andreas Färber, 2013/06/29
- [Qemu-devel] [PATCH RFC qom-cpu 35/41] cpu: Introduce CPUClass::memory_rw_debug() for target_memory_rw_debug(),
Andreas Färber <=
- [Qemu-devel] [PATCH RFC qom-cpu 36/41] gdbstub: Change GDBState::g_cpu to CPUState, Andreas Färber, 2013/06/29
- [Qemu-devel] [PATCH RFC qom-cpu 34/41] exec: Change cpu_memory_rw_debug() argument to CPUState, Andreas Färber, 2013/06/29
- [Qemu-devel] [PATCH RFC qom-cpu 37/41] cpu: Move gdb_regs field from CPU_COMMON to CPUState, Andreas Färber, 2013/06/29
- [Qemu-devel] [PATCH RFC qom-cpu 38/41] gdbstub: Change gdb_register_coprocessor() argument to CPUState, Andreas Färber, 2013/06/29
- [Qemu-devel] [PATCH RFC qom-cpu 33/41] cpu: Turn cpu_get_phys_page_debug() into a CPUClass hook, Andreas Färber, 2013/06/29
- [Qemu-devel] [PATCH RFC qom-cpu 40/41] gdbstub: Move num_g_regs to CPUState and NUM_CORE_REGS to CPUClass, Andreas Färber, 2013/06/29
- [Qemu-devel] [PATCH RFC qom-cpu 39/41] target-xtensa: Introduce XtensaCPU subclasses, Andreas Färber, 2013/06/29
- [Qemu-devel] [PATCH RFC qom-cpu 41/41] cpu: Introduce CPUClass::gdb_{read, write}_register(), Andreas Färber, 2013/06/29
- Re: [Qemu-devel] [PATCH RFC qom-cpu 00/41] QOM CPUState, part 11: GDB stub, Michael Walle, 2013/06/30