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Re: [Qemu-devel] [PATCH v3 11/14] ioport: Switch dispatching to memory c
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH v3 11/14] ioport: Switch dispatching to memory core layer |
Date: |
Sun, 14 Jul 2013 17:50:49 +0100 |
On 14 July 2013 16:18, Anthony Liguori <address@hidden> wrote:
> On Sun, Jul 14, 2013 at 9:58 AM, Peter Maydell <address@hidden> wrote:
>> Devices themselves do have a byte order, though, right? Specifically,
>> if you do a 32 bit read of address 0 on a device and an 8 bit read,
>
> It depends on the bus and device. Busses don't necessary pass the I/O
> size down to the device like that. If it does, the device may do any
> number of things (including ignoring the request entirely.
Agreed.
> What's most common AFAIK is that the access is treated as a word
> access and then truncated. IOW, the device sees the 32-bit word read
> but somewhere along the way, the top 24 bits are discarded.
>
> The real interesting question is what happens when you do a byte
> access at address 1. I think most devices simply don't allow that.
Mmm, and where it is permitted it's going to be device dependent
(for instance the ARM GIC has most registers be 32-bit access only,
with a few which allow 8-bit access; and the GIC spec states that
those byte accesses use a little endian memory order model).
It looks like most of the ARM PLxxx devices on the APB bus simply
don't wire up address lines 0 and 1, so an access to address 1
will behave like one to address 0. (Of course we don't model this.)
-- PMM
- Re: [Qemu-devel] [Qemu-ppc] [PATCH v3 11/14] ioport: Switch dispatching to memory core layer, (continued)
- Re: [Qemu-devel] [Qemu-ppc] [PATCH v3 11/14] ioport: Switch dispatching to memory core layer, Peter Maydell, 2013/07/15
- Re: [Qemu-devel] [Qemu-ppc] [PATCH v3 11/14] ioport: Switch dispatching to memory core layer, Benjamin Herrenschmidt, 2013/07/15
- Re: [Qemu-devel] [Qemu-ppc] [PATCH v3 11/14] ioport: Switch dispatching to memory core layer, Benjamin Herrenschmidt, 2013/07/12
- Re: [Qemu-devel] [PATCH v3 11/14] ioport: Switch dispatching to memory core layer, Paolo Bonzini, 2013/07/13
- Re: [Qemu-devel] [PATCH v3 11/14] ioport: Switch dispatching to memory core layer, Anthony Liguori, 2013/07/13
- Re: [Qemu-devel] [PATCH v3 11/14] ioport: Switch dispatching to memory core layer, Hervé Poussineau, 2013/07/13
- Re: [Qemu-devel] [PATCH v3 11/14] ioport: Switch dispatching to memory core layer, Paolo Bonzini, 2013/07/14
- Re: [Qemu-devel] [PATCH v3 11/14] ioport: Switch dispatching to memory core layer, Anthony Liguori, 2013/07/14
- Re: [Qemu-devel] [PATCH v3 11/14] ioport: Switch dispatching to memory core layer, Peter Maydell, 2013/07/14
- Re: [Qemu-devel] [PATCH v3 11/14] ioport: Switch dispatching to memory core layer, Anthony Liguori, 2013/07/14
- Re: [Qemu-devel] [PATCH v3 11/14] ioport: Switch dispatching to memory core layer,
Peter Maydell <=
- Re: [Qemu-devel] [PATCH v3 11/14] ioport: Switch dispatching to memory core layer, Jan Kiszka, 2013/07/16
- Re: [Qemu-devel] [PATCH v3 11/14] ioport: Switch dispatching to memory core layer, Paolo Bonzini, 2013/07/16
- Re: [Qemu-devel] [PATCH v3 11/14] ioport: Switch dispatching to memory core layer, Hervé Poussineau, 2013/07/16
- Re: [Qemu-devel] [PATCH v3 11/14] ioport: Switch dispatching to memory core layer, Paolo Bonzini, 2013/07/16
Re: [Qemu-devel] [PATCH v3 11/14] ioport: Switch dispatching to memory core layer, Anthony Liguori, 2013/07/12
[Qemu-devel] BUG: Re: [PATCH v3 11/14] ioport: Switch dispatching to memory core layer, Alexey Kardashevskiy, 2013/07/19