Re: [Qemu-devel] [PATCH 05/17] pseries: savevm support for XICS interrupt controller

[Paolo Bonzini]

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Il 09/07/2013 09:17, David Gibson ha scritto:
> So, Alexey addressed the xics vs. xics-kvm issues.  But there's 
> another factor here.  It's not clear to me how you'd QOM this 
> component.
> 
> What's being registered here is the "presentation server".  That's
> the per-CPU part - vaguely equivalent to the LAPIC on x86.  x86
> doesn't have something equivalent here, because they register the
> LAPIC state as part of the CPU state, but we can't do that because
> the ICP is not bound to the CPU as tightly - a POWER7 using a
> different interrupt architecture would certainly be possible.

That's also possible with x86, in fact there is a command line option
to only use the legacy 8259 interrupt controller.

The LAPIC is a separate device from the CPU, it just happens that the
CPU also needs a back-pointer to the LAPIC.  If you do not need that
back-pointer, just do not put it in.  The ICP can still have a link
property that points to the CPU.

Paolo

> So to do this with QOM, would the ICP need to be registered as a
> child of the cpu object?

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