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[Qemu-devel] [PATCH for-next 08/15] tcg-ppc64: Create PowerOpcode
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH for-next 08/15] tcg-ppc64: Create PowerOpcode |
Date: |
Mon, 5 Aug 2013 08:28:43 -1000 |
This makes some bits easier to debug, being presented with a symbol
instead of a number inside gdb.
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/ppc64/tcg-target.c | 273 +++++++++++++++++++++++++------------------------
1 file changed, 138 insertions(+), 135 deletions(-)
diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c
index 862e84c..a79b876 100644
--- a/tcg/ppc64/tcg-target.c
+++ b/tcg/ppc64/tcg-target.c
@@ -313,133 +313,10 @@ static int tcg_target_const_match (tcg_target_long val,
#define XO58(opc) (OPCD(58)|(opc))
#define XO62(opc) (OPCD(62)|(opc))
-#define B OPCD( 18)
-#define BC OPCD( 16)
-#define LBZ OPCD( 34)
-#define LHZ OPCD( 40)
-#define LHA OPCD( 42)
-#define LWZ OPCD( 32)
-#define STB OPCD( 38)
-#define STH OPCD( 44)
-#define STW OPCD( 36)
-
-#define STD XO62( 0)
-#define STDU XO62( 1)
-#define STDX XO31(149)
-
-#define LD XO58( 0)
-#define LDX XO31( 21)
-#define LDU XO58( 1)
-#define LWA XO58( 2)
-#define LWAX XO31(341)
-
-#define ADDIC OPCD( 12)
-#define ADDI OPCD( 14)
-#define ADDIS OPCD( 15)
-#define ORI OPCD( 24)
-#define ORIS OPCD( 25)
-#define XORI OPCD( 26)
-#define XORIS OPCD( 27)
-#define ANDI OPCD( 28)
-#define ANDIS OPCD( 29)
-#define MULLI OPCD( 7)
-#define CMPLI OPCD( 10)
-#define CMPI OPCD( 11)
-#define SUBFIC OPCD( 8)
-
-#define LWZU OPCD( 33)
-#define STWU OPCD( 37)
-
-#define RLWIMI OPCD( 20)
-#define RLWINM OPCD( 21)
-#define RLWNM OPCD( 23)
-
-#define RLDICL MD30( 0)
-#define RLDICR MD30( 1)
-#define RLDIMI MD30( 3)
-#define RLDCL MDS30( 8)
-
-#define BCLR XO19( 16)
-#define BCCTR XO19(528)
-#define CRAND XO19(257)
-#define CRANDC XO19(129)
-#define CRNAND XO19(225)
-#define CROR XO19(449)
-#define CRNOR XO19( 33)
-
-#define EXTSB XO31(954)
-#define EXTSH XO31(922)
-#define EXTSW XO31(986)
-#define ADD XO31(266)
-#define ADDE XO31(138)
-#define ADDME XO31(234)
-#define ADDZE XO31(202)
-#define ADDC XO31( 10)
-#define AND XO31( 28)
-#define SUBF XO31( 40)
-#define SUBFC XO31( 8)
-#define SUBFE XO31(136)
-#define SUBFME XO31(232)
-#define SUBFZE XO31(200)
-#define OR XO31(444)
-#define XOR XO31(316)
-#define MULLW XO31(235)
-#define MULHWU XO31( 11)
-#define DIVW XO31(491)
-#define DIVWU XO31(459)
-#define CMP XO31( 0)
-#define CMPL XO31( 32)
-#define LHBRX XO31(790)
-#define LWBRX XO31(534)
-#define LDBRX XO31(532)
-#define STHBRX XO31(918)
-#define STWBRX XO31(662)
-#define STDBRX XO31(660)
-#define MFSPR XO31(339)
-#define MTSPR XO31(467)
-#define SRAWI XO31(824)
-#define NEG XO31(104)
-#define MFCR XO31( 19)
-#define MFOCRF (MFCR | (1u << 20))
-#define NOR XO31(124)
-#define CNTLZW XO31( 26)
-#define CNTLZD XO31( 58)
-#define ANDC XO31( 60)
-#define ORC XO31(412)
-#define EQV XO31(284)
-#define NAND XO31(476)
-#define ISEL XO31( 15)
-
-#define MULLD XO31(233)
-#define MULHD XO31( 73)
-#define MULHDU XO31( 9)
-#define DIVD XO31(489)
-#define DIVDU XO31(457)
-
-#define LBZX XO31( 87)
-#define LHZX XO31(279)
-#define LHAX XO31(343)
-#define LWZX XO31( 23)
-#define STBX XO31(215)
-#define STHX XO31(407)
-#define STWX XO31(151)
-
#define SPR(a,b) ((((a)<<5)|(b))<<11)
#define LR SPR(8, 0)
#define CTR SPR(9, 0)
-#define SLW XO31( 24)
-#define SRW XO31(536)
-#define SRAW XO31(792)
-
-#define SLD XO31( 27)
-#define SRD XO31(539)
-#define SRAD XO31(794)
-#define SRADI XO31(413<<1)
-
-#define TW XO31( 4)
-#define TRAP (TW | TO (31))
-
#define RT(r) ((r)<<21)
#define RS(r) ((r)<<21)
#define RA(r) ((r)<<16)
@@ -455,6 +332,131 @@ static int tcg_target_const_match (tcg_target_long val,
#define LK 1
#define AA 2
+typedef enum PowerOpcode {
+ B = OPCD( 18),
+ BC = OPCD( 16),
+ LBZ = OPCD( 34),
+ LHZ = OPCD( 40),
+ LHA = OPCD( 42),
+ LWZ = OPCD( 32),
+ STB = OPCD( 38),
+ STH = OPCD( 44),
+ STW = OPCD( 36),
+
+ STD = XO62( 0),
+ STDU = XO62( 1),
+ STDX = XO31(149),
+
+ LD = XO58( 0),
+ LDX = XO31( 21),
+ LDU = XO58( 1),
+ LWA = XO58( 2),
+ LWAX = XO31(341),
+
+ ADDIC = OPCD( 12),
+ ADDI = OPCD( 14),
+ ADDIS = OPCD( 15),
+ ORI = OPCD( 24),
+ ORIS = OPCD( 25),
+ XORI = OPCD( 26),
+ XORIS = OPCD( 27),
+ ANDI = OPCD( 28),
+ ANDIS = OPCD( 29),
+ MULLI = OPCD( 7),
+ CMPLI = OPCD( 10),
+ CMPI = OPCD( 11),
+ SUBFIC = OPCD( 8),
+
+ LWZU = OPCD( 33),
+ STWU = OPCD( 37),
+
+ RLWIMI = OPCD( 20),
+ RLWINM = OPCD( 21),
+ RLWNM = OPCD( 23),
+
+ RLDICL = MD30( 0),
+ RLDICR = MD30( 1),
+ RLDIMI = MD30( 3),
+ RLDCL = MDS30( 8),
+
+ BCLR = XO19( 16),
+ BCCTR = XO19(528),
+ CRAND = XO19(257),
+ CRANDC = XO19(129),
+ CRNAND = XO19(225),
+ CROR = XO19(449),
+ CRNOR = XO19( 33),
+
+ EXTSB = XO31(954),
+ EXTSH = XO31(922),
+ EXTSW = XO31(986),
+ ADD = XO31(266),
+ ADDE = XO31(138),
+ ADDME = XO31(234),
+ ADDZE = XO31(202),
+ ADDC = XO31( 10),
+ AND = XO31( 28),
+ SUBF = XO31( 40),
+ SUBFC = XO31( 8),
+ SUBFE = XO31(136),
+ SUBFME = XO31(232),
+ SUBFZE = XO31(200),
+ OR = XO31(444),
+ XOR = XO31(316),
+ MULLW = XO31(235),
+ MULHWU = XO31( 11),
+ DIVW = XO31(491),
+ DIVWU = XO31(459),
+ CMP = XO31( 0),
+ CMPL = XO31( 32),
+ LHBRX = XO31(790),
+ LWBRX = XO31(534),
+ LDBRX = XO31(532),
+ STHBRX = XO31(918),
+ STWBRX = XO31(662),
+ STDBRX = XO31(660),
+ MFSPR = XO31(339),
+ MTSPR = XO31(467),
+ SRAWI = XO31(824),
+ NEG = XO31(104),
+ MFCR = XO31( 19),
+ MFOCRF = MFCR | (1u << 20),
+ NOR = XO31(124),
+ CNTLZW = XO31( 26),
+ CNTLZD = XO31( 58),
+ ANDC = XO31( 60),
+ ORC = XO31(412),
+ EQV = XO31(284),
+ NAND = XO31(476),
+ ISEL = XO31( 15),
+
+ MULLD = XO31(233),
+ MULHD = XO31( 73),
+ MULHDU = XO31( 9),
+ DIVD = XO31(489),
+ DIVDU = XO31(457),
+
+ LBZX = XO31( 87),
+ LHZX = XO31(279),
+ LHAX = XO31(343),
+ LWZX = XO31( 23),
+ STBX = XO31(215),
+ STHX = XO31(407),
+ STWX = XO31(151),
+
+ SLW = XO31( 24),
+ SRW = XO31(536),
+ SRAW = XO31(792),
+
+ SLD = XO31( 27),
+ SRD = XO31(539),
+ SRAD = XO31(794),
+ SRADI = XO31(413<<1),
+
+ TW = XO31( 4),
+ TRAP = TW | TO(31),
+} PowerOpcode;
+
#define TAB(t, a, b) (RT(t) | RA(a) | RB(b))
#define SAB(s, a, b) (RS(s) | RA(a) | RB(b))
#define TAI(s, a, i) (RT(s) | RA(a) | ((i) & 0xffff))
@@ -513,16 +515,16 @@ static inline void tcg_out_mov(TCGContext *s, TCGType
type,
}
}
-static inline void tcg_out_rld(TCGContext *s, int op, TCGReg ra, TCGReg rs,
- int sh, int mb)
+static inline void tcg_out_rld(TCGContext *s, PowerOpcode op, TCGReg ra,
+ TCGReg rs, int sh, int mb)
{
sh = SH (sh & 0x1f) | (((sh >> 5) & 1) << 1);
mb = MB64 ((mb >> 5) | ((mb << 1) & 0x3f));
tcg_out32 (s, op | RA (ra) | RS (rs) | sh | mb);
}
-static inline void tcg_out_rlw(TCGContext *s, int op, TCGReg ra, TCGReg rs,
- int sh, int mb, int me)
+static inline void tcg_out_rlw(TCGContext *s, PowerOpcode op, TCGReg ra,
+ TCGReg rs, int sh, int mb, int me)
{
tcg_out32(s, op | RA(ra) | RS(rs) | SH(sh) | MB(mb) | ME(me));
}
@@ -666,7 +668,7 @@ static void tcg_out_andi64(TCGContext *s, TCGReg dst,
TCGReg src, uint64_t c)
}
static void tcg_out_zori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c,
- int op_lo, int op_hi)
+ PowerOpcode op_lo, PowerOpcode op_hi)
{
if (c >> 16) {
tcg_out32(s, op_hi | SAI(src, dst, c >> 16));
@@ -741,7 +743,7 @@ static void tcg_out_call(TCGContext *s, tcg_target_long arg,
}
static void tcg_out_ldst(TCGContext *s, TCGReg ret, TCGReg addr,
- int offset, int op1, int op2)
+ int offset, PowerOpcode op1, PowerOpcode op2)
{
if (offset == (int16_t) offset) {
tcg_out32(s, op1 | TAI(ret, addr, offset));
@@ -752,7 +754,7 @@ static void tcg_out_ldst(TCGContext *s, TCGReg ret, TCGReg
addr,
}
static void tcg_out_ldsta(TCGContext *s, TCGReg ret, TCGReg addr,
- int offset, int op1, int op2)
+ int offset, PowerOpcode op1, PowerOpcode op2)
{
if (offset == (int16_t) (offset & ~3)) {
tcg_out32(s, op1 | TAI(ret, addr, offset));
@@ -820,7 +822,7 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg r0,
TCGReg r1, TCGReg r2,
}
#endif
-static const uint32_t qemu_ldx_opc[8] = {
+static const PowerOpcode qemu_ldx_opc[8] = {
#ifdef TARGET_WORDS_BIGENDIAN
LBZX, LHZX, LWZX, LDX,
0, LHAX, LWAX, LDX
@@ -830,7 +832,7 @@ static const uint32_t qemu_ldx_opc[8] = {
#endif
};
-static const uint32_t qemu_stx_opc[4] = {
+static const PowerOpcode qemu_stx_opc[4] = {
#ifdef TARGET_WORDS_BIGENDIAN
STBX, STHX, STWX, STDX
#else
@@ -838,14 +840,15 @@ static const uint32_t qemu_stx_opc[4] = {
#endif
};
-static const uint32_t qemu_exts_opc[4] = {
+static const PowerOpcode qemu_exts_opc[4] = {
EXTSB, EXTSH, EXTSW, 0
};
static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
{
TCGReg addr_reg, data_reg, r0, r1, rbase;
- uint32_t insn, s_bits;
+ PowerOpcode insn;
+ int s_bits;
#ifdef CONFIG_SOFTMMU
TCGReg r2, ir;
int mem_index;
@@ -936,7 +939,7 @@ static void tcg_out_qemu_ld (TCGContext *s, const TCGArg
*args, int opc)
static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
{
TCGReg addr_reg, r0, r1, rbase, data_reg;
- uint32_t insn;
+ PowerOpcode insn;
#ifdef CONFIG_SOFTMMU
TCGReg r2, ir;
int mem_index;
--
1.8.3.1
- [Qemu-devel] [PATCH for-next 00/15] Collection of improvements for tcg/ppc64, Richard Henderson, 2013/08/05
- [Qemu-devel] [PATCH for-next 01/15] tcg-ppc64: Avoid code for nop move, Richard Henderson, 2013/08/05
- [Qemu-devel] [PATCH for-next 02/15] tcg-ppc64: Add an LK argument to tcg_out_call, Richard Henderson, 2013/08/05
- [Qemu-devel] [PATCH for-next 03/15] tcg-ppc64: Use the branch absolute instruction when possible, Richard Henderson, 2013/08/05
- [Qemu-devel] [PATCH for-next 04/15] tcg-ppc64: Don't load the static chain from TCG, Richard Henderson, 2013/08/05
- [Qemu-devel] [PATCH for-next 05/15] tcg-ppc64: Look through the function descriptor when profitable, Richard Henderson, 2013/08/05
- [Qemu-devel] [PATCH for-next 06/15] tcg-ppc64: Move AREG0 to r31, Richard Henderson, 2013/08/05
- [Qemu-devel] [PATCH for-next 07/15] tcg-ppc64: Tidy register allocation order, Richard Henderson, 2013/08/05
- [Qemu-devel] [PATCH for-next 08/15] tcg-ppc64: Create PowerOpcode,
Richard Henderson <=
- [Qemu-devel] [PATCH for-next 09/15] tcg-ppc64: Handle long offsets better, Richard Henderson, 2013/08/05
- [Qemu-devel] [PATCH for-next 10/15] tcg-ppc64: Use indirect jump threading, Richard Henderson, 2013/08/05
- [Qemu-devel] [PATCH for-next 11/15] tcg-ppc64: Setup TCG_REG_TB, Richard Henderson, 2013/08/05
- [Qemu-devel] [PATCH for-next 12/15] tcg-ppc64: Use TCG_REG_TB in tcg_out_movi and tcg_out_mem_long, Richard Henderson, 2013/08/05
- [Qemu-devel] [PATCH for-next 14/15] tcg-ppc64: Streamline tcg_out_tlb_read, Richard Henderson, 2013/08/05
- [Qemu-devel] [PATCH for-next 15/15] tcg-ppc64: Implement CONFIG_QEMU_LDST_OPTIMIZATION, Richard Henderson, 2013/08/05
- [Qemu-devel] [PATCH for-next 13/15] tcg-ppc64: Tidy tcg_target_qemu_prologue, Richard Henderson, 2013/08/05
- Re: [Qemu-devel] [PATCH for-next 00/15] Collection of improvements for tcg/ppc64, Richard Henderson, 2013/08/17