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[Qemu-devel] [PATCH 09/16] tcg-mips: Use TCGMemOp within qemu_ldst routi
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 09/16] tcg-mips: Use TCGMemOp within qemu_ldst routines |
Date: |
Wed, 4 Sep 2013 14:04:58 -0700 |
Untested.
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/mips/tcg-target.c | 116 ++++++++++++++++++++++----------------------------
1 file changed, 52 insertions(+), 64 deletions(-)
diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
index 5f0a65b..3ef5487 100644
--- a/tcg/mips/tcg-target.c
+++ b/tcg/mips/tcg-target.c
@@ -24,12 +24,6 @@
* THE SOFTWARE.
*/
-#if defined(TCG_TARGET_WORDS_BIGENDIAN) == defined(TARGET_WORDS_BIGENDIAN)
-# define TCG_NEED_BSWAP 0
-#else
-# define TCG_NEED_BSWAP 1
-#endif
-
#ifndef NDEBUG
static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
"zero",
@@ -938,10 +932,11 @@ static const void * const qemu_st_helpers[4] = {
};
#endif
-static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
- int opc)
+static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, TCGMemOp opc)
{
TCGReg addr_regl, data_regl, data_regh, data_reg1, data_reg2;
+ TCGMemOp s_bits = opc & MO_SIZE;
+ TCGMemOp bswap = opc & MO_BSWAP;
#if defined(CONFIG_SOFTMMU)
void *label1_ptr, *label2_ptr;
int arg_num;
@@ -954,10 +949,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg
*args,
# endif
#endif
data_regl = *args++;
- if (opc == 3)
- data_regh = *args++;
- else
- data_regh = 0;
+ data_regh = (s_bits == MO_64 ? *args++ : 0);
addr_regl = *args++;
#if defined(CONFIG_SOFTMMU)
# if TARGET_LONG_BITS == 64
@@ -973,10 +965,9 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg
*args,
addr_meml = 0;
# endif
mem_index = *args;
- s_bits = opc & 3;
#endif
- if (opc == 3) {
+ if (s_bits == MO_64) {
#if defined(TCG_TARGET_WORDS_BIGENDIAN)
data_reg1 = data_regh;
data_reg2 = data_regl;
@@ -988,6 +979,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg
*args,
data_reg1 = data_regl;
data_reg2 = 0;
}
+
#if defined(CONFIG_SOFTMMU)
tcg_out_opc_sa(s, OPC_SRL, TCG_REG_A0, addr_regl, TARGET_PAGE_BITS -
CPU_TLB_ENTRY_BITS);
tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_A0, TCG_REG_A0, (CPU_TLB_SIZE - 1) <<
CPU_TLB_ENTRY_BITS);
@@ -1029,23 +1021,23 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg
*args,
tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_REG_T9, 0);
tcg_out_nop(s);
- switch(opc) {
- case 0:
+ switch (opc & MO_SSIZE) {
+ case MO_UB:
tcg_out_opc_imm(s, OPC_ANDI, data_reg1, TCG_REG_V0, 0xff);
break;
- case 0 | 4:
+ case MO_SB:
tcg_out_ext8s(s, data_reg1, TCG_REG_V0);
break;
- case 1:
+ case MO_UW:
tcg_out_opc_imm(s, OPC_ANDI, data_reg1, TCG_REG_V0, 0xffff);
break;
- case 1 | 4:
+ case MO_SW:
tcg_out_ext16s(s, data_reg1, TCG_REG_V0);
break;
- case 2:
+ case MO_UL:
tcg_out_mov(s, TCG_TYPE_I32, data_reg1, TCG_REG_V0);
break;
- case 3:
+ case MO_Q:
tcg_out_mov(s, TCG_TYPE_I32, data_reg2, TCG_REG_V1);
tcg_out_mov(s, TCG_TYPE_I32, data_reg1, TCG_REG_V0);
break;
@@ -1072,39 +1064,39 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg
*args,
}
#endif
- switch(opc) {
- case 0:
+ switch (opc & MO_SSIZE) {
+ case MO_UB:
tcg_out_opc_imm(s, OPC_LBU, data_reg1, TCG_REG_V0, 0);
break;
- case 0 | 4:
+ case MO_SB:
tcg_out_opc_imm(s, OPC_LB, data_reg1, TCG_REG_V0, 0);
break;
- case 1:
- if (TCG_NEED_BSWAP) {
+ case MO_UW:
+ if (bswap) {
tcg_out_opc_imm(s, OPC_LHU, TCG_REG_T0, TCG_REG_V0, 0);
tcg_out_bswap16(s, data_reg1, TCG_REG_T0);
} else {
tcg_out_opc_imm(s, OPC_LHU, data_reg1, TCG_REG_V0, 0);
}
break;
- case 1 | 4:
- if (TCG_NEED_BSWAP) {
+ case MO_SW:
+ if (bswap) {
tcg_out_opc_imm(s, OPC_LHU, TCG_REG_T0, TCG_REG_V0, 0);
tcg_out_bswap16s(s, data_reg1, TCG_REG_T0);
} else {
tcg_out_opc_imm(s, OPC_LH, data_reg1, TCG_REG_V0, 0);
}
break;
- case 2:
- if (TCG_NEED_BSWAP) {
+ case MO_UL:
+ if (bswap) {
tcg_out_opc_imm(s, OPC_LW, TCG_REG_T0, TCG_REG_V0, 0);
tcg_out_bswap32(s, data_reg1, TCG_REG_T0);
} else {
tcg_out_opc_imm(s, OPC_LW, data_reg1, TCG_REG_V0, 0);
}
break;
- case 3:
- if (TCG_NEED_BSWAP) {
+ case MO_Q:
+ if (bswap) {
tcg_out_opc_imm(s, OPC_LW, TCG_REG_T0, TCG_REG_V0, 4);
tcg_out_bswap32(s, data_reg1, TCG_REG_T0);
tcg_out_opc_imm(s, OPC_LW, TCG_REG_T0, TCG_REG_V0, 0);
@@ -1123,10 +1115,11 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg
*args,
#endif
}
-static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
- int opc)
+static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, TCGMemOp opc)
{
TCGReg addr_regl, data_regl, data_regh, data_reg1, data_reg2;
+ TCGMemOp s_bits = opc & MO_SIZE;
+ TCGMemOp bswap = opc & MO_BSWAP;
#if defined(CONFIG_SOFTMMU)
uint8_t *label1_ptr, *label2_ptr;
int arg_num;
@@ -1141,11 +1134,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg
*args,
# endif
#endif
data_regl = *args++;
- if (opc == 3) {
- data_regh = *args++;
- } else {
- data_regh = 0;
- }
+ data_regh = (s_bits == MO_64 ? *args++ : 0);
addr_regl = *args++;
#if defined(CONFIG_SOFTMMU)
# if TARGET_LONG_BITS == 64
@@ -1161,10 +1150,9 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg
*args,
addr_meml = 0;
# endif
mem_index = *args;
- s_bits = opc;
#endif
- if (opc == 3) {
+ if (s_bits == MO_64) {
#if defined(TCG_TARGET_WORDS_BIGENDIAN)
data_reg1 = data_regh;
data_reg2 = data_regl;
@@ -1213,17 +1201,17 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg
*args,
# else
tcg_out_call_iarg_reg32(s, &arg_num, addr_regl);
# endif
- switch(opc) {
- case 0:
+ switch (s_bits) {
+ case MO_8:
tcg_out_call_iarg_reg8(s, &arg_num, data_regl);
break;
- case 1:
+ case MO_16:
tcg_out_call_iarg_reg16(s, &arg_num, data_regl);
break;
- case 2:
+ case MO_32:
tcg_out_call_iarg_reg32(s, &arg_num, data_regl);
break;
- case 3:
+ case MO_64:
tcg_out_call_iarg_reg64(s, &arg_num, data_regl, data_regh);
break;
default:
@@ -1254,12 +1242,12 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg
*args,
#endif
- switch(opc) {
- case 0:
+ switch (s_bits) {
+ case MO_8:
tcg_out_opc_imm(s, OPC_SB, data_reg1, TCG_REG_A0, 0);
break;
- case 1:
- if (TCG_NEED_BSWAP) {
+ case MO_16:
+ if (bswap) {
tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_T0, data_reg1, 0xffff);
tcg_out_bswap16(s, TCG_REG_T0, TCG_REG_T0);
tcg_out_opc_imm(s, OPC_SH, TCG_REG_T0, TCG_REG_A0, 0);
@@ -1267,16 +1255,16 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg
*args,
tcg_out_opc_imm(s, OPC_SH, data_reg1, TCG_REG_A0, 0);
}
break;
- case 2:
- if (TCG_NEED_BSWAP) {
+ case MO_32:
+ if (bswap) {
tcg_out_bswap32(s, TCG_REG_T0, data_reg1);
tcg_out_opc_imm(s, OPC_SW, TCG_REG_T0, TCG_REG_A0, 0);
} else {
tcg_out_opc_imm(s, OPC_SW, data_reg1, TCG_REG_A0, 0);
}
break;
- case 3:
- if (TCG_NEED_BSWAP) {
+ case MO_64:
+ if (bswap) {
tcg_out_bswap32(s, TCG_REG_T0, data_reg2);
tcg_out_opc_imm(s, OPC_SW, TCG_REG_T0, TCG_REG_A0, 0);
tcg_out_bswap32(s, TCG_REG_T0, data_reg1);
@@ -1550,34 +1538,34 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode
opc,
break;
case INDEX_op_qemu_ld8u:
- tcg_out_qemu_ld(s, args, 0);
+ tcg_out_qemu_ld(s, args, MO_UB);
break;
case INDEX_op_qemu_ld8s:
- tcg_out_qemu_ld(s, args, 0 | 4);
+ tcg_out_qemu_ld(s, args, MO_SB);
break;
case INDEX_op_qemu_ld16u:
- tcg_out_qemu_ld(s, args, 1);
+ tcg_out_qemu_ld(s, args, MO_TEUW);
break;
case INDEX_op_qemu_ld16s:
- tcg_out_qemu_ld(s, args, 1 | 4);
+ tcg_out_qemu_ld(s, args, MO_TESW);
break;
case INDEX_op_qemu_ld32:
- tcg_out_qemu_ld(s, args, 2);
+ tcg_out_qemu_ld(s, args, MO_TEUL);
break;
case INDEX_op_qemu_ld64:
- tcg_out_qemu_ld(s, args, 3);
+ tcg_out_qemu_ld(s, args, MO_TEQ);
break;
case INDEX_op_qemu_st8:
- tcg_out_qemu_st(s, args, 0);
+ tcg_out_qemu_st(s, args, MO_UB);
break;
case INDEX_op_qemu_st16:
- tcg_out_qemu_st(s, args, 1);
+ tcg_out_qemu_st(s, args, MO_TEUW);
break;
case INDEX_op_qemu_st32:
- tcg_out_qemu_st(s, args, 2);
+ tcg_out_qemu_st(s, args, MO_TEUL);
break;
case INDEX_op_qemu_st64:
- tcg_out_qemu_st(s, args, 3);
+ tcg_out_qemu_st(s, args, MO_TEQ);
break;
default:
--
1.8.1.4
- [Qemu-devel] [PATCH 00/16] Streamlining endian handling in TCG, Richard Henderson, 2013/09/04
- [Qemu-devel] [PATCH 03/16] tcg-aarch64: Use TCGMemOp within qemu_ldst routines, Richard Henderson, 2013/09/04
- [Qemu-devel] [PATCH 04/16] tcg-arm: Use TCGMemOp within qemu_ldst routines, Richard Henderson, 2013/09/04
- [Qemu-devel] [PATCH 02/16] tcg-i386: Use TCGMemOp within qemu_ldst routines, Richard Henderson, 2013/09/04
- [Qemu-devel] [PATCH 01/16] tcg: Add TCGMemOp, Richard Henderson, 2013/09/04
- [Qemu-devel] [PATCH 05/16] tcg-s390: Use TCGMemOp within qemu_ldst routines, Richard Henderson, 2013/09/04
- [Qemu-devel] [PATCH 06/16] tcg-ppc: Use TCGMemOp within qemu_ldst routines, Richard Henderson, 2013/09/04
- [Qemu-devel] [PATCH 07/16] tcg-ppc64: Use TCGMemOp within qemu_ldst routines, Richard Henderson, 2013/09/04
- [Qemu-devel] [PATCH 08/16] tcg-hppa: Use TCGMemOp within qemu_ldst routines, Richard Henderson, 2013/09/04
- [Qemu-devel] [PATCH 09/16] tcg-mips: Use TCGMemOp within qemu_ldst routines,
Richard Henderson <=
- [Qemu-devel] [PATCH 10/16] tcg-sparc: Use TCGMemOp within qemu_ldst routines, Richard Henderson, 2013/09/04
- [Qemu-devel] [PATCH 11/16] tcg: Add qemu_ld_st_i32/64, Richard Henderson, 2013/09/04
- [Qemu-devel] [PATCH 12/16] exec: Add both big- and little-endian memory helpers, Richard Henderson, 2013/09/04
- [Qemu-devel] [PATCH 14/16] tcg-i386: Remove "cb" output restriction from qemu_st8 for i386, Richard Henderson, 2013/09/04
- [Qemu-devel] [PATCH 13/16] tcg-i386: Tidy softmmu routines, Richard Henderson, 2013/09/04
- [Qemu-devel] [PATCH 15/16] tcg-i386: Support new ldst opcodes, Richard Henderson, 2013/09/04
- [Qemu-devel] [PATCH 16/16] target-ppc: Convert to new ldst opcodes, Richard Henderson, 2013/09/04