Re: [Qemu-devel] [PATCH RFC v2 2/2] hw/pci: handle unassigned pci addresses

[Peter Maydell]

On 15 September 2013 16:05, Michael S. Tsirkin <address@hidden> wrote:
> On Sun, Sep 15, 2013 at 03:49:00PM +0100, Peter Maydell wrote:
>> On 15 September 2013 15:20, Michael S. Tsirkin <address@hidden> wrote:
>> > Actually you previosly wrote:
>> >         > the versatilePB's PCI controller only responds to accesses
>> >         > within its programmed MMIO BAR ranges, so if the device
>> >         > or the controller have been misconfigured you can get an
>> >         > abort when the device tries to do DMA.
>> > Doesn't this mean versatilePB will have to have
>> > similar code in it's PCI controller implementation -
>> > outside PCI controller core?
>>
>> If you implement PCI bus mastering sufficiently accurately in the
>> PCI core code, then maybe not
>
> Well it's not about implementation I think:
> RAM is not on the PCI bus, is it?

A PCI device can only do DMA to RAM if the versatile
host controller is configured so that (a) it has mapped its
BARs into the PCI memory space somewhere and (b)
the host controller's mapping from BARs to system
addresses means device access to the host controller
BARs turn into accesses to system addresses where
the RAM is.

> If it's not on the PCI bus I doubt RAM accesses
> can cause master aborts on the PCI bus: PCI host
> would have to claim and then possibly discard them.

The aborts I refer to above are if you misprogram the
device to try to do a bus master access to some part of
PCI memory space other than where the host controller's
BARs are (or if you misprogram the controller not to
map its BARs at all).

> Well PCI device access to another PCI device looks
> differently depending on whether the other device
> is on the same bus, or not.
>
> When it's on the same bus, device detects master abort.
> When it's on a different bus (across a bridge),
> bridge detects master abort, device detects completion.

Yeah, but this is all PCI core code, not controller specific.

-- PMM