[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH 19/60] AArch64: Add ins GPR->Vec instruction emulati
From: |
Alexander Graf |
Subject: |
[Qemu-devel] [PATCH 19/60] AArch64: Add ins GPR->Vec instruction emulation |
Date: |
Fri, 27 Sep 2013 02:48:13 +0200 |
This patch adds emulation for the INS instruction flavor that copies
GPR contents into vector register parts.
Signed-off-by: Alexander Graf <address@hidden>
---
target-arm/translate-a64.c | 39 +++++++++++++++++++++++++++++++++++++++
1 file changed, 39 insertions(+)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index e29d5a8..546ca13 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -922,6 +922,42 @@ static void handle_umov(DisasContext *s, uint32_t insn)
}
}
+static void handle_insg(DisasContext *s, uint32_t insn)
+{
+ int rd = get_bits(insn, 0, 5);
+ int rn = get_bits(insn, 5, 5);
+ int imm5 = get_bits(insn, 16, 6);
+ int freg_offs_d = offsetof(CPUARMState, vfp.regs[rd * 2]);
+ int size;
+ int idx;
+
+ for (size = 0; !(imm5 & (1 << size)); size++) {
+ if (size > 3) {
+ unallocated_encoding(s);
+ return;
+ }
+ }
+
+ switch (size) {
+ case 0:
+ idx = get_bits(imm5, 1, 4) << 0;
+ tcg_gen_st8_i64(cpu_reg(rn), cpu_env, freg_offs_d + idx);
+ break;
+ case 1:
+ idx = get_bits(imm5, 2, 3) << 1;
+ tcg_gen_st16_i64(cpu_reg(rn), cpu_env, freg_offs_d + idx);
+ break;
+ case 2:
+ idx = get_bits(imm5, 3, 2) << 2;
+ tcg_gen_st32_i64(cpu_reg(rn), cpu_env, freg_offs_d + idx);
+ break;
+ case 3:
+ idx = get_bits(imm5, 4, 1) << 3;
+ tcg_gen_st_i64(cpu_reg(rn), cpu_env, freg_offs_d + idx);
+ break;
+ }
+}
+
void disas_a64_insn(CPUARMState *env, DisasContext *s)
{
uint32_t insn;
@@ -987,6 +1023,9 @@ void disas_a64_insn(CPUARMState *env, DisasContext *s)
} else if (!get_bits(insn, 31, 1) && !get_bits(insn, 29, 1) &&
(get_bits(insn, 10, 6) == 0xf)) {
handle_umov(s, insn);
+ } else if ((get_bits(insn, 29, 3) == 2) && !get_bits(insn, 21, 3) &&
+ (get_bits(insn, 10, 6) == 0x7)) {
+ handle_insg(s, insn);
} else {
unallocated_encoding(s);
}
--
1.7.12.4
- [Qemu-devel] [PATCH 09/60] AArch64: Add b and bl handling, (continued)
- [Qemu-devel] [PATCH 09/60] AArch64: Add b and bl handling, Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 08/60] AArch64: Add support to print VFP registers in CPU, Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 22/60] AArch64: Add AdvSIMD scalar three same group handling, Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 11/60] AArch64: Add STP instruction emulation, Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 04/60] arm: Add AArch64 disassembler stub, Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 19/60] AArch64: Add ins GPR->Vec instruction emulation,
Alexander Graf <=
- [Qemu-devel] [PATCH 07/60] ARM: Add 64bit VFP handling, Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 06/60] AArch64: Add set_pc cpu method, Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 15/60] AArch64: Add add instruction family emulation, Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 17/60] AArch64: Add dup GPR->Vec instruction emulation, Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 24/60] AArch64: Add SIMD ushll instruction emulation, Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 26/60] AArch64: Add ADR instruction emulation, Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 20/60] AArch64: Add SIMD ORR family instruction emulation, Alexander Graf, 2013/09/26