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[Qemu-devel] [PATCH for-1.8 41/61] target_i386: Clean up gen_pop_T0
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH for-1.8 41/61] target_i386: Clean up gen_pop_T0 |
Date: |
Thu, 7 Nov 2013 11:05:04 +1000 |
Reduce ifdefs, share more code between paths, reduce the number of TCG
ops generated. Avoid re-computing the size of the operation across
gen_pop_T0 and gen_pop_update.
Add forgotten zero-extension in the TARGET_X86_64, !CODE64, ss32 case.
Signed-off-by: Richard Henderson <address@hidden>
---
target-i386/translate.c | 84 ++++++++++++++++++++++---------------------------
1 file changed, 37 insertions(+), 47 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 77ed32e..135f573 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -2420,30 +2420,30 @@ static void gen_push_v(DisasContext *s, TCGv val)
}
/* two step pop is necessary for precise exceptions */
-static void gen_pop_T0(DisasContext *s)
+static TCGMemOp gen_pop_T0(DisasContext *s)
{
-#ifdef TARGET_X86_64
+ TCGMemOp d_ot = mo_pushpop(s, s->dflag);
+ TCGv addr = cpu_A0;
+
if (CODE64(s)) {
- gen_op_movq_A0_reg(R_ESP);
- gen_op_ld_v(s, mo_pushpop(s, s->dflag), cpu_T[0], cpu_A0);
- } else
-#endif
- {
- gen_op_movl_A0_reg(R_ESP);
- if (s->ss32) {
- if (s->addseg)
- gen_op_addl_A0_seg(s, R_SS);
- } else {
- tcg_gen_ext16u_tl(cpu_A0, cpu_A0);
- gen_op_addl_A0_seg(s, R_SS);
- }
- gen_op_ld_v(s, s->dflag, cpu_T[0], cpu_A0);
+ addr = cpu_regs[R_ESP];
+ } else if (!s->ss32) {
+ tcg_gen_ext16u_tl(cpu_A0, cpu_regs[R_ESP]);
+ gen_op_addl_A0_seg(s, R_SS);
+ } else if (s->addseg) {
+ tcg_gen_mov_tl(cpu_A0, cpu_regs[R_ESP]);
+ gen_op_addl_A0_seg(s, R_SS);
+ } else {
+ tcg_gen_ext32u_tl(cpu_A0, cpu_regs[R_ESP]);
}
+
+ gen_op_ld_v(s, d_ot, cpu_T[0], addr);
+ return d_ot;
}
-static void gen_pop_update(DisasContext *s)
+static void gen_pop_update(DisasContext *s, TCGMemOp ot)
{
- gen_stack_update(s, 1 << mo_pushpop(s, s->dflag));
+ gen_stack_update(s, 1 << ot);
}
static void gen_stack_A0(DisasContext *s)
@@ -5239,10 +5239,9 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
gen_push_v(s, cpu_T[0]);
break;
case 0x58 ... 0x5f: /* pop */
- ot = mo_pushpop(s, dflag);
- gen_pop_T0(s);
+ ot = gen_pop_T0(s);
/* NOTE: order is important for pop %sp */
- gen_pop_update(s);
+ gen_pop_update(s, ot);
gen_op_mov_reg_T0(ot, (b & 7) | REX_B(s));
break;
case 0x60: /* pusha */
@@ -5266,13 +5265,12 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
gen_push_v(s, cpu_T[0]);
break;
case 0x8f: /* pop Ev */
- ot = mo_pushpop(s, dflag);
modrm = cpu_ldub_code(env, s->pc++);
mod = (modrm >> 6) & 3;
- gen_pop_T0(s);
+ ot = gen_pop_T0(s);
if (mod == 3) {
/* NOTE: order is important for pop %sp */
- gen_pop_update(s);
+ gen_pop_update(s, ot);
rm = (modrm & 7) | REX_B(s);
gen_op_mov_reg_T0(ot, rm);
} else {
@@ -5280,7 +5278,7 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
s->popl_esp_hack = 1 << ot;
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
s->popl_esp_hack = 0;
- gen_pop_update(s);
+ gen_pop_update(s, ot);
}
break;
case 0xc8: /* enter */
@@ -5304,10 +5302,9 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
gen_op_mov_TN_reg(MO_16, 0, R_EBP);
gen_op_mov_reg_T0(MO_16, R_ESP);
}
- gen_pop_T0(s);
- ot = mo_pushpop(s, dflag);
+ ot = gen_pop_T0(s);
gen_op_mov_reg_T0(ot, R_EBP);
- gen_pop_update(s);
+ gen_pop_update(s, ot);
break;
case 0x06: /* push es */
case 0x0e: /* push cs */
@@ -5329,9 +5326,9 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
if (CODE64(s))
goto illegal_op;
reg = b >> 3;
- gen_pop_T0(s);
+ ot = gen_pop_T0(s);
gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
- gen_pop_update(s);
+ gen_pop_update(s, ot);
if (reg == R_SS) {
/* if reg == SS, inhibit interrupts/trace. */
/* If several instructions disable interrupts, only the
@@ -5347,9 +5344,9 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
break;
case 0x1a1: /* pop fs */
case 0x1a9: /* pop gs */
- gen_pop_T0(s);
+ ot = gen_pop_T0(s);
gen_movl_seg_T0(s, (b >> 3) & 7, pc_start - s->cs_base);
- gen_pop_update(s);
+ gen_pop_update(s, ot);
if (s->is_jmp) {
gen_jmp_im(s->pc - s->cs_base);
gen_eob(s);
@@ -6385,23 +6382,16 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
case 0xc2: /* ret im */
val = cpu_ldsw_code(env, s->pc);
s->pc += 2;
- gen_pop_T0(s);
- if (CODE64(s) && dflag != MO_16) {
- dflag = MO_64;
- }
- gen_stack_update(s, val + (1 << dflag));
- if (dflag == MO_16) {
- tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
- }
+ ot = gen_pop_T0(s);
+ gen_stack_update(s, val + (1 << ot));
+ /* Note that gen_pop_T0 uses a zero-extending load. */
gen_op_jmp_T0();
gen_eob(s);
break;
case 0xc3: /* ret */
- gen_pop_T0(s);
- gen_pop_update(s);
- if (dflag == MO_16) {
- tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
- }
+ ot = gen_pop_T0(s);
+ gen_pop_update(s, ot);
+ /* Note that gen_pop_T0 uses a zero-extending load. */
gen_op_jmp_T0();
gen_eob(s);
break;
@@ -6574,7 +6564,7 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
if (s->vm86 && s->iopl != 3) {
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
} else {
- gen_pop_T0(s);
+ ot = gen_pop_T0(s);
if (s->cpl == 0) {
if (dflag != MO_16) {
gen_helper_write_eflags(cpu_env, cpu_T[0],
@@ -6620,7 +6610,7 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
}
}
}
- gen_pop_update(s);
+ gen_pop_update(s, ot);
set_cc_op(s, CC_OP_EFLAGS);
/* abort translation because TF/AC flag may change */
gen_jmp_im(s->pc - s->cs_base);
--
1.8.3.1
- [Qemu-devel] [PATCH for-1.8 29/61] target-i386: Remove gen_op_andl_T0_im, (continued)
- [Qemu-devel] [PATCH for-1.8 29/61] target-i386: Remove gen_op_andl_T0_im, Richard Henderson, 2013/11/06
- [Qemu-devel] [PATCH for-1.8 30/61] target-i386: Remove gen_op_movl_T0_T1, Richard Henderson, 2013/11/06
- [Qemu-devel] [PATCH for-1.8 31/61] target-i386: Remove gen_op_andl_A0_ffff, Richard Henderson, 2013/11/06
- [Qemu-devel] [PATCH for-1.8 32/61] target-i386: Use TCGMemOp for 'ot' variables, Richard Henderson, 2013/11/06
- [Qemu-devel] [PATCH for-1.8 33/61] target-i386: Change gen_op_add_reg_* size parameter to TCGMemOp, Richard Henderson, 2013/11/06
- [Qemu-devel] [PATCH for-1.8 34/61] target-i386: Change gen_op_j*z_ecx size parameter to TCGMemOp, Richard Henderson, 2013/11/06
- [Qemu-devel] [PATCH for-1.8 37/61] target-i386: Change dflag to TCGMemOp, Richard Henderson, 2013/11/06
- [Qemu-devel] [PATCH for-1.8 38/61] target-i386: Fix addr32 prefix in gen_lea_modrm, Richard Henderson, 2013/11/06
- [Qemu-devel] [PATCH for-1.8 39/61] target-i386: Tidy addr16 code in gen_lea_modrm, Richard Henderson, 2013/11/06
- [Qemu-devel] [PATCH for-1.8 40/61] target-i386: Combine gen_push_T* into gen_push_v, Richard Henderson, 2013/11/06
- [Qemu-devel] [PATCH for-1.8 41/61] target_i386: Clean up gen_pop_T0,
Richard Henderson <=
- [Qemu-devel] [PATCH for-1.8 42/61] target-i386: Create gen_lea_v_seg, Richard Henderson, 2013/11/06
- [Qemu-devel] [PATCH for-1.8 43/61] target-i386: Use gen_lea_v_seg in gen_lea_modrm, Richard Henderson, 2013/11/06
- [Qemu-devel] [PATCH for-1.8 44/61] target-i386: Use gen_lea_v_seg in stack subroutines, Richard Henderson, 2013/11/06
- [Qemu-devel] [PATCH for-1.8 45/61] target-i386: Tidy cpu_regs initialization, Richard Henderson, 2013/11/06
- [Qemu-devel] [PATCH for-1.8 46/61] target-i386: Access segs via TCG registers, Richard Henderson, 2013/11/06
- [Qemu-devel] [PATCH for-1.8 49/61] target-i386: Introduce mo_stacksize, Richard Henderson, 2013/11/06
- [Qemu-devel] [PATCH for-1.8 50/61] target-i386: Rewrite leave, Richard Henderson, 2013/11/06
- [Qemu-devel] [PATCH for-1.8 51/61] target-i386: Remove gen_op_mov_reg_T0, Richard Henderson, 2013/11/06
- [Qemu-devel] [PATCH for-1.8 52/61] target-i386: Remove gen_op_mov_reg_T1, Richard Henderson, 2013/11/06
- [Qemu-devel] [PATCH for-1.8 53/61] target-i386: Remove gen_op_addl_T0_T1, Richard Henderson, 2013/11/06