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[Qemu-devel] [PULL 1/7] target-openrisc: Speed up move instruction
From: |
Jia Liu |
Subject: |
[Qemu-devel] [PULL 1/7] target-openrisc: Speed up move instruction |
Date: |
Wed, 20 Nov 2013 22:38:32 +0800 |
From: Sebastian Macke <address@hidden>
The OpenRISC architecture does not have its own move register
instruction. Instead it uses either "l.addi rd, r0, x" or
"l.ori rd, rs, 0" or "l.or rd, rx, r0"
The l.ori instruction is automatically optimized but not the l.addi instruction.
This patch optimizes for this special case.
Signed-off-by: Sebastian Macke <address@hidden>
Reviewed-by: Jia Liu <address@hidden>
Signed-off-by: Jia Liu <address@hidden>
---
target-openrisc/translate.c | 50 ++++++++++++++++++++++++---------------------
1 file changed, 27 insertions(+), 23 deletions(-)
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index 8908a2e..8276ce7 100644
--- a/target-openrisc/translate.c
+++ b/target-openrisc/translate.c
@@ -904,29 +904,33 @@ static void dec_misc(DisasContext *dc, uint32_t insn)
case 0x27: /* l.addi */
LOG_DIS("l.addi r%d, r%d, %d\n", rd, ra, I16);
{
- int lab = gen_new_label();
- TCGv_i64 ta = tcg_temp_new_i64();
- TCGv_i64 td = tcg_temp_local_new_i64();
- TCGv_i32 res = tcg_temp_local_new_i32();
- TCGv_i32 sr_ove = tcg_temp_local_new_i32();
- tcg_gen_extu_i32_i64(ta, cpu_R[ra]);
- tcg_gen_addi_i64(td, ta, sign_extend(I16, 16));
- tcg_gen_trunc_i64_i32(res, td);
- tcg_gen_shri_i64(td, td, 32);
- tcg_gen_andi_i64(td, td, 0x3);
- /* Jump to lab when no overflow. */
- tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x0, lab);
- tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x3, lab);
- tcg_gen_ori_i32(cpu_sr, cpu_sr, (SR_OV | SR_CY));
- tcg_gen_andi_i32(sr_ove, cpu_sr, SR_OVE);
- tcg_gen_brcondi_i32(TCG_COND_NE, sr_ove, SR_OVE, lab);
- gen_exception(dc, EXCP_RANGE);
- gen_set_label(lab);
- tcg_gen_mov_i32(cpu_R[rd], res);
- tcg_temp_free_i64(ta);
- tcg_temp_free_i64(td);
- tcg_temp_free_i32(res);
- tcg_temp_free_i32(sr_ove);
+ if (I16 == 0) {
+ tcg_gen_mov_tl(cpu_R[rd], cpu_R[ra]);
+ } else {
+ int lab = gen_new_label();
+ TCGv_i64 ta = tcg_temp_new_i64();
+ TCGv_i64 td = tcg_temp_local_new_i64();
+ TCGv_i32 res = tcg_temp_local_new_i32();
+ TCGv_i32 sr_ove = tcg_temp_local_new_i32();
+ tcg_gen_extu_i32_i64(ta, cpu_R[ra]);
+ tcg_gen_addi_i64(td, ta, sign_extend(I16, 16));
+ tcg_gen_trunc_i64_i32(res, td);
+ tcg_gen_shri_i64(td, td, 32);
+ tcg_gen_andi_i64(td, td, 0x3);
+ /* Jump to lab when no overflow. */
+ tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x0, lab);
+ tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x3, lab);
+ tcg_gen_ori_i32(cpu_sr, cpu_sr, (SR_OV | SR_CY));
+ tcg_gen_andi_i32(sr_ove, cpu_sr, SR_OVE);
+ tcg_gen_brcondi_i32(TCG_COND_NE, sr_ove, SR_OVE, lab);
+ gen_exception(dc, EXCP_RANGE);
+ gen_set_label(lab);
+ tcg_gen_mov_i32(cpu_R[rd], res);
+ tcg_temp_free_i64(ta);
+ tcg_temp_free_i64(td);
+ tcg_temp_free_i32(res);
+ tcg_temp_free_i32(sr_ove);
+ }
}
break;
--
1.8.3.4 (Apple Git-47)
- [Qemu-devel] [PULL 0/7] OpenRISC patch queue for 1.7, Jia Liu, 2013/11/20
- [Qemu-devel] [PULL 3/7] target-openrisc: Remove executable flag for every page, Jia Liu, 2013/11/20
- [Qemu-devel] [PULL 4/7] target-openrisc: Correct wrong epcr register in interrupt handler, Jia Liu, 2013/11/20
- [Qemu-devel] [PULL 5/7] openrisc-timer: Reduce overhead, Separate clock update functions, Jia Liu, 2013/11/20
- [Qemu-devel] [PULL 6/7] target-openrisc: Correct memory bounds checking for the tlb buffers, Jia Liu, 2013/11/20
- [Qemu-devel] [PULL 7/7] target-openrisc: Correct carry flag check of l.addc and l.addic test cases, Jia Liu, 2013/11/20
- [Qemu-devel] [PULL 1/7] target-openrisc: Speed up move instruction,
Jia Liu <=
- [Qemu-devel] [PULL 2/7] target-openrisc: Remove unnecessary code generated by jump instructions, Jia Liu, 2013/11/20