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Re: [Qemu-devel] [PATCH 01/13] target-arm: A64: add support for conditio
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH 01/13] target-arm: A64: add support for conditional select |
Date: |
Fri, 6 Dec 2013 17:23:40 +0000 |
On 6 December 2013 16:44, Richard Henderson <address@hidden> wrote:
> On 12/07/2013 01:45 AM, Peter Maydell wrote:
>> On 5 December 2013 22:26, Richard Henderson <address@hidden> wrote:
>>> On 12/06/2013 10:51 AM, Peter Maydell wrote:
>>>> + if (cond >= 0x0e) { /* condition "always" */
>>>> + tcg_src = read_cpu_reg(s, rn, sf);
>>>> + tcg_gen_mov_i64(tcg_rd, tcg_src);
>>>
>>> I wonder if it's worth adding that 0x0[ef] case to the generic condition
>>> processing rather than keep replicating it everywhere.
>>
>> I think "always true" is a special case anyway because you don't
>> want to emit any kind of branching/label logic at all.
>
> Sure, but unlike unconditional branches, which are useful to special-case, one
> sort of expects never to see an unconditional conditional move. Given
> TCG_COND_ALWAYS, we can re-use generic logic and have things fall out
> relatively easily.
I guess. It doesn't seem much worth adding extra code to arm_gen_test_cc
that we expect to become redundant if/when we do these insns "properly"
with setcond/movcond, though, so I think it's OK like this for now.
thanks
-- PMM
- [Qemu-devel] [PATCH 13/13] target-arm: A64: add support for logical (immediate) insns, (continued)
[Qemu-devel] [PATCH 11/13] host-utils: add clrsb32/64 - count leading redundant sign bits, Peter Maydell, 2013/12/05
[Qemu-devel] [PATCH 07/13] target-arm: A64: add support for 1-src data processing and CLZ, Peter Maydell, 2013/12/05
[Qemu-devel] [PATCH 05/13] target-arm: A64: add support for 2-src data processing and DIV, Peter Maydell, 2013/12/05