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From: | Xin Tong |
Subject: | Re: [Qemu-devel] outlined TLB lookup on x86 |
Date: | Sun, 8 Dec 2013 02:54:53 -0800 |
Xin Tong writes:There was some discussion long ago about adding vector instructions to TCG, but
> Hi LIuis
> we can probably generate vector intrinsics using the tcg, e.g. add support to
> tcg to emit vector instructions directly in code cache
I don't remember what was the conclusion.
Also remember that using vector instructions will "emulate" a low-associativity
TLB; don't know how much better than a 1-way TLB will that be, though.
It would make TLB invalidations slower (e.g., see 'tlb_flush' in
> why would a larger TLB make some operations slower, the TLB is a direct-mapped
> hash and lookup should be O(1) there. In the cputlb, the CPU_TLB_SIZE is always
> used to index into the TLB, i.e. (X & (CPU_TLB_SIZE -1)).
"cputlb.c"). And right now QEMU performs full TLB invalidations more frequently
than the equivalent HW needs to, although I suppose that should be quantified
too.
Lluis
--
"And it's much the same thing with knowledge, for whenever you learn
something new, the whole world becomes that much richer."
-- The Princess of Pure Reason, as told by Norton Juster in The Phantom
Tollbooth
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