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[Qemu-devel] [PATCH 0/9] target-arm: A64 decoder set 3: loads, stores, m
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 0/9] target-arm: A64 decoder set 3: loads, stores, misc integer |
Date: |
Mon, 9 Dec 2013 18:12:14 +0000 |
Welcome back to the latest installment in this thrilling
series of A64 decoder patches. In this episode, we have:
* support for most kinds of load and store (still to come are
load-literal, the exclusives and the SIMD structure ld/st)
* addition and subtraction (but not adc/sbc)
* some other minor integer instructions
(Tune in next time for set 4, which is likely to contain
FMOV, the user-space permitted parts of MSR/MRS, load
literal, and exclusives; since that's sufficient to get
through libc startup and run simple binaries we'll also
throw in the 'actually enable the target' patches.)
Git tree (with v7-cpu-host/mach-virt, v8 kvm control,
and A64 set one & two all underneath these patches):
git://git.linaro.org/people/peter.maydell/qemu-arm.git a64-third-set
web UI:
https://git.linaro.org/people/peter.maydell/qemu-arm.git/shortlog/refs/heads/a64-second-set
thanks
-- PMM
Alex Bennée (7):
target-arm: A64: add support for stp (store pair)
target-arm: A64: add support for ldp (load pair)
target-arm: A64: add support for ld/st unsigned imm
target-arm: A64: add support for ld/st with reg offset
target-arm: A64: add support for ld/st with index
target-arm: A64: add support for add, addi, sub, subi
target-arm: A64: add support for move wide instructions
Alexander Graf (2):
target-arm: A64: add support for 3 src data proc insns
target-arm: A64: implement SVC, BRK
target-arm/helper-a64.c | 14 +
target-arm/helper-a64.h | 2 +
target-arm/translate-a64.c | 1255 +++++++++++++++++++++++++++++++++++++++++++-
3 files changed, 1251 insertions(+), 20 deletions(-)
--
1.8.5
- [Qemu-devel] [PATCH 0/9] target-arm: A64 decoder set 3: loads, stores, misc integer,
Peter Maydell <=