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[Qemu-devel] [PULL 05/37] cpu/a9mpcore: Add Global Timer
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 05/37] cpu/a9mpcore: Add Global Timer |
Date: |
Tue, 10 Dec 2013 14:43:01 +0000 |
From: François LEGAL <address@hidden>
Add the global timer to A9 MPCore.
Signed-off-by: François LEGAL <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
[PC Changes:
* new commit message
* split off original version as a separate patch
* Rebased against new mpcore implementation (with struct embedding)
]
Signed-off-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
hw/cpu/a9mpcore.c | 26 +++++++++++++++++++++-----
include/hw/cpu/a9mpcore.h | 2 ++
2 files changed, 23 insertions(+), 5 deletions(-)
diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c
index a38464b..c09358c 100644
--- a/hw/cpu/a9mpcore.c
+++ b/hw/cpu/a9mpcore.c
@@ -30,6 +30,9 @@ static void a9mp_priv_initfn(Object *obj)
object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC);
qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default());
+ object_initialize(&s->gtimer, sizeof(s->gtimer), TYPE_A9_GTIMER);
+ qdev_set_parent_bus(DEVICE(&s->gtimer), sysbus_get_default());
+
object_initialize(&s->mptimer, sizeof(s->mptimer), TYPE_ARM_MPTIMER);
qdev_set_parent_bus(DEVICE(&s->mptimer), sysbus_get_default());
@@ -41,8 +44,9 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp)
{
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
A9MPPrivState *s = A9MPCORE_PRIV(dev);
- DeviceState *scudev, *gicdev, *mptimerdev, *wdtdev;
- SysBusDevice *scubusdev, *gicbusdev, *mptimerbusdev, *wdtbusdev;
+ DeviceState *scudev, *gicdev, *gtimerdev, *mptimerdev, *wdtdev;
+ SysBusDevice *scubusdev, *gicbusdev, *gtimerbusdev, *mptimerbusdev,
+ *wdtbusdev;
Error *err = NULL;
int i;
@@ -71,6 +75,15 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp)
/* Pass through inbound GPIO lines to the GIC */
qdev_init_gpio_in(dev, a9mp_priv_set_irq, s->num_irq - 32);
+ gtimerdev = DEVICE(&s->gtimer);
+ qdev_prop_set_uint32(gtimerdev, "num-cpu", s->num_cpu);
+ object_property_set_bool(OBJECT(&s->gtimer), true, "realized", &err);
+ if (err != NULL) {
+ error_propagate(errp, err);
+ return;
+ }
+ gtimerbusdev = SYS_BUS_DEVICE(&s->gtimer);
+
mptimerdev = DEVICE(&s->mptimer);
qdev_prop_set_uint32(mptimerdev, "num-cpu", s->num_cpu);
object_property_set_bool(OBJECT(&s->mptimer), true, "realized", &err);
@@ -97,14 +110,14 @@ static void a9mp_priv_realize(DeviceState *dev, Error
**errp)
* 0x0600-0x06ff -- private timers and watchdogs
* 0x0700-0x0fff -- nothing
* 0x1000-0x1fff -- GIC Distributor
- *
- * We should implement the global timer but don't currently do so.
*/
memory_region_add_subregion(&s->container, 0,
sysbus_mmio_get_region(scubusdev, 0));
/* GIC CPU interface */
memory_region_add_subregion(&s->container, 0x100,
sysbus_mmio_get_region(gicbusdev, 1));
+ memory_region_add_subregion(&s->container, 0x200,
+ sysbus_mmio_get_region(gtimerbusdev, 0));
/* Note that the A9 exposes only the "timer/watchdog for this core"
* memory region, not the "timer/watchdog for core X" ones 11MPcore has.
*/
@@ -116,10 +129,13 @@ static void a9mp_priv_realize(DeviceState *dev, Error
**errp)
sysbus_mmio_get_region(gicbusdev, 0));
/* Wire up the interrupt from each watchdog and timer.
- * For each core the timer is PPI 29 and the watchdog PPI 30.
+ * For each core the global timer is PPI 27, the private
+ * timer is PPI 29 and the watchdog PPI 30.
*/
for (i = 0; i < s->num_cpu; i++) {
int ppibase = (s->num_irq - 32) + i * 32;
+ sysbus_connect_irq(gtimerbusdev, i,
+ qdev_get_gpio_in(gicdev, ppibase + 27));
sysbus_connect_irq(mptimerbusdev, i,
qdev_get_gpio_in(gicdev, ppibase + 29));
sysbus_connect_irq(wdtbusdev, i,
diff --git a/include/hw/cpu/a9mpcore.h b/include/hw/cpu/a9mpcore.h
index 8eece07..5d67ca2 100644
--- a/include/hw/cpu/a9mpcore.h
+++ b/include/hw/cpu/a9mpcore.h
@@ -14,6 +14,7 @@
#include "hw/intc/arm_gic.h"
#include "hw/misc/a9scu.h"
#include "hw/timer/arm_mptimer.h"
+#include "hw/timer/a9gtimer.h"
#define TYPE_A9MPCORE_PRIV "a9mpcore_priv"
#define A9MPCORE_PRIV(obj) \
@@ -30,6 +31,7 @@ typedef struct A9MPPrivState {
A9SCUState scu;
GICState gic;
+ A9GTimerState gtimer;
ARMMPTimerState mptimer;
ARMMPTimerState wdt;
} A9MPPrivState;
--
1.8.5
- [Qemu-devel] [PULL 25/37] net/cadence_gem: Fix rx multi-fragment packets, (continued)
- [Qemu-devel] [PULL 25/37] net/cadence_gem: Fix rx multi-fragment packets, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 19/37] net/cadence_gem: simplify rx buf descriptor walking, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 15/37] hw/arm/virt: Support -cpu host, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 06/37] target-arm: Provide mechanism for getting KVM constants even if not CONFIG_KVM, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 12/37] hw/arm: Add 'virt' platform, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 30/37] target-arm: Move call to disas_vfp_insn out of disas_coproc_insn., Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 07/37] device_tree.c: Terminate the empty reservemap in create_device_tree(), Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 04/37] hw/timer: Introduce ARM A9 Global Timer., Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 20/37] net/cadence_gem: Prefetch rx descriptors ASAP, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 01/37] integrator/cp: add support for REFCNT register, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 05/37] cpu/a9mpcore: Add Global Timer,
Peter Maydell <=
- [Qemu-devel] [PULL 08/37] hw/arm/boot: Allow boards to provide an fdt blob, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 23/37] net/cadence_gem: Implement SAR (de)activation, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 14/37] target-arm: Provide '-cpu host' when running KVM, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 13/37] target-arm: Don't hardcode KVM target CPU to be A15, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 21/37] net/cadence_gem: Implement RX descriptor match mode flags, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 37/37] target-arm: fix TTBCR write masking, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 18/37] net/cadence_gem: Don't assert against 0 buffer address, Peter Maydell, 2013/12/10