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Re: [Qemu-devel] [PATCH v3 7/8] target-arm: A64: add support for 3 src d
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH v3 7/8] target-arm: A64: add support for 3 src data proc insns |
Date: |
Mon, 16 Dec 2013 10:49:23 +0000 |
On 13 December 2013 19:18, Peter Maydell <address@hidden> wrote:
> static void disas_data_proc_3src(DisasContext *s, uint32_t insn)
> {
> - unsupported_encoding(s, insn);
> + int rd = extract32(insn, 0, 5);
> + int rn = extract32(insn, 5, 5);
> + int ra = extract32(insn, 10, 5);
> + int rm = extract32(insn, 16, 5);
> + int op_id = (extract32(insn, 29, 3) << 4) |
> + (extract32(insn, 21, 3) << 1) |
> + extract32(insn, 15, 1);
> + bool is_32bit = !extract32(insn, 31, 1);
> + bool is_sub = extract32(op_id, 0, 1);
> + bool is_high = extract32(op_id, 2, 1);
> + bool is_signed = false;
> + TCGv_i64 tcg_op1;
> + TCGv_i64 tcg_op2;
> + TCGv_i64 tcg_tmp;
> +
> + /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag
> */
> + switch (op_id) {
> + case 0x42: /* SMADDL */
> + case 0x43: /* SMSUBL */
> + case 0x44: /* SMULH */
> + is_signed = true;
> + break;
> + case 0x0: /* MADD (32bit) */
> + case 0x1: /* MSUB (32bit) */
> + case 0x40: /* MADD (64bit) */
> + case 0x41: /* MSUB (64bit) */
> + case 0x4a: /* UMADDL */
> + case 0x4b: /* UMSUBL */
> + case 0x4c: /* UMULH */
> + break;
> + default:
> + unallocated_encoding(s);
> + }
Missing 'return' after unallocated_encoding(), fixed in my
working tree.
thanks
-- PMM
- [Qemu-devel] [PATCH v3 0/8] target-arm: A64 decoder set 3: loads, stores, misc integer, Peter Maydell, 2013/12/13
- [Qemu-devel] [PATCH v3 7/8] target-arm: A64: add support for 3 src data proc insns, Peter Maydell, 2013/12/13
- [Qemu-devel] [PATCH v3 2/8] target-arm: A64: add support for ld/st unsigned imm, Peter Maydell, 2013/12/13
- [Qemu-devel] [PATCH v3 8/8] target-arm: A64: implement SVC, BRK, Peter Maydell, 2013/12/13
- [Qemu-devel] [PATCH v3 1/8] target-arm: A64: add support for ld/st pair, Peter Maydell, 2013/12/13
- [Qemu-devel] [PATCH v3 6/8] target-arm: A64: add support for move wide instructions, Peter Maydell, 2013/12/13
- [Qemu-devel] [PATCH v3 5/8] target-arm: A64: add support for add, addi, sub, subi, Peter Maydell, 2013/12/13
- [Qemu-devel] [PATCH v3 4/8] target-arm: A64: add support for ld/st with index, Peter Maydell, 2013/12/13
- [Qemu-devel] [PATCH v3 3/8] target-arm: A64: add support for ld/st with reg offset, Peter Maydell, 2013/12/13