Re: [Qemu-devel] [PATCH 11/21] target-arm: Update generic cpreg code for AArch64

[Peter Maydell]

On 20 December 2013 22:07, Peter Maydell <address@hidden> wrote:
> On 20 December 2013 21:41, Peter Crosthwaite
> <address@hidden> wrote:
>> On Sat, Dec 21, 2013 at 4:16 AM, Peter Maydell <address@hidden> wrote:
>>>  * for the few registers which aren't neatly arranged so the
>>>    crn/crm/opc1/opc2 line up, we just split up into a separate
>>>    reginfo for AArch64 and AArch32
>>
>> ACK, that sounds awkward but there nothing we can do abt it. how many
>> are there? The few I checked always line up.
>
> Well, everything in cp14 doesn't have architectural equivalents,
> for a start. In AArch32 TCMTR is crn=0 crm=0 opc1=0 opc2=2
> but that is OSDTRRX_EL1 in AArch64. The TLB and cache
> maintenance ops don't always match up because they've been
> tidied up, I think. The docs don't make it terribly easy to compile
> a list of mismatches though.

More generally I think the way that AArch64 uses op1 to group
the registers by exception-level-access-rights is going to make it
a bit tricky to do the mapping; we either need to
(1) have .opc1 be the AA32 opc1 and infer AA64 op1 from
the permission flags
(2) have .opc1 be the AA64 op1 and insist that the AA32 opc1
is always zero  (or always same as AA64 op1?), and require
split reginfo structs if this isn't so
(3) have both op1 and opc1 fields in the reginfo struct

I don't much like any of these but I guess (2) is least worst.

-- PMM