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[Qemu-devel] [PATCH 20/22] target-arm: A64: Add floating-point<->integer
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 20/22] target-arm: A64: Add floating-point<->integer conversion instructions |
Date: |
Tue, 31 Dec 2013 13:35:56 +0000 |
From: Will Newton <address@hidden>
Add support for the AArch64 floating-point <-> integer conversion
instructions to disas_fpintconv. In the process we can rearrange
and simplify the detection of unallocated encodings a little.
We also correct a typo in the instruction encoding diagram for this
instruction group: bit 21 is 1, not 0.
Signed-off-by: Will Newton <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/translate-a64.c | 23 ++++++++++++++++++++---
1 file changed, 20 insertions(+), 3 deletions(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index ec8abc7..9b23d37 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -3904,7 +3904,7 @@ static void handle_fmov(DisasContext *s, int rd, int rn,
int type, bool itof)
/* C3.6.30 Floating point <-> integer conversions
* 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
* +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
- * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
+ * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
* +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
*/
static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
@@ -3917,10 +3917,20 @@ static void disas_fp_int_conv(DisasContext *s, uint32_t
insn)
bool sbit = extract32(insn, 29, 1);
bool sf = extract32(insn, 31, 1);
- if (!sbit && (rmode < 2) && (opcode > 5)) {
+ if (sbit) {
+ unallocated_encoding(s);
+ return;
+ }
+
+ if (opcode > 5) {
/* FMOV */
bool itof = opcode & 1;
+ if (rmode >= 2) {
+ unallocated_encoding(s);
+ return;
+ }
+
switch (sf << 3 | type << 1 | rmode) {
case 0x0: /* 32 bit */
case 0xa: /* 64 bit */
@@ -3935,7 +3945,14 @@ static void disas_fp_int_conv(DisasContext *s, uint32_t
insn)
handle_fmov(s, rd, rn, type, itof);
} else {
/* actual FP conversions */
- unsupported_encoding(s, insn);
+ bool itof = extract32(opcode, 1, 1);
+
+ if (type > 1 || (rmode != 0 && opcode > 1)) {
+ unallocated_encoding(s);
+ return;
+ }
+
+ handle_fpfpcvt(s, rd, rn, opcode, itof, rmode, 64, sf, type);
}
}
--
1.8.5
- Re: [Qemu-devel] [PATCH 03/22] softfloat: Add 16 bit integer to float conversions, (continued)
[Qemu-devel] [PATCH 11/22] softfloat: Provide complete set of accessors for fp state, Peter Maydell, 2013/12/31
[Qemu-devel] [PATCH 15/22] target-arm: Prepare VFP_CONV_FIX helpers for A64 uses, Peter Maydell, 2013/12/31
[Qemu-devel] [PATCH 08/22] softfloat: Fix float64_to_uint64_round_to_zero, Peter Maydell, 2013/12/31
[Qemu-devel] [PATCH 20/22] target-arm: A64: Add floating-point<->integer conversion instructions,
Peter Maydell <=
[Qemu-devel] [PATCH 01/22] softfloat: Fix exception flag handling for float32_to_float16(), Peter Maydell, 2013/12/31
[Qemu-devel] [PATCH 02/22] softfloat: Add float to 16bit integer conversions., Peter Maydell, 2013/12/31
[Qemu-devel] [PATCH 22/22] target-arm: A64: Add support for FCVT between half, single and double, Peter Maydell, 2013/12/31
[Qemu-devel] [PATCH 16/22] target-arm: Rename A32 VFP conversion helpers, Peter Maydell, 2013/12/31
[Qemu-devel] [PATCH 10/22] softfloat: Fix float64_to_uint32_round_to_zero, Peter Maydell, 2013/12/31