[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH target-arm v2 09/11] char/cadence_uart: Use the TX f
From: |
Peter Crosthwaite |
Subject: |
[Qemu-devel] [PATCH target-arm v2 09/11] char/cadence_uart: Use the TX fifo for transmission |
Date: |
Wed, 1 Jan 2014 18:03:11 -0800 |
Populate the TxFIFO with the Tx data before sending. Prepares
support for proper Tx flow control implementation.
Signed-off-by: Peter Crosthwaite <address@hidden>
---
hw/char/cadence_uart.c | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
index 3bcaf29..be32126 100644
--- a/hw/char/cadence_uart.c
+++ b/hw/char/cadence_uart.c
@@ -292,7 +292,22 @@ static void uart_write_tx_fifo(UartState *s, const uint8_t
*buf, int size)
return;
}
- qemu_chr_fe_write_all(s->chr, buf, size);
+ if (size > TX_FIFO_SIZE - s->tx_count) {
+ size = TX_FIFO_SIZE - s->tx_count;
+ /*
+ * This can only be a guest error via a bad tx fifo register push,
+ * as can_receive() should stop remote loop and echo modes ever getting
+ * us to here.
+ */
+ qemu_log_mask(LOG_GUEST_ERROR, "cadence_uart: TxFIFO overflow");
+ s->r[R_CISR] |= UART_INTR_ROVR;
+ }
+
+ memcpy(s->tx_fifo + s->tx_count, buf, size);
+ s->tx_count += size;
+
+ qemu_chr_fe_write_all(s->chr, s->tx_fifo, s->tx_count);
+ s->tx_count = 0;
}
static void uart_receive(void *opaque, const uint8_t *buf, int size)
--
1.8.5.2
- [Qemu-devel] [PATCH target-arm v2 00/11] Cadence UART cleanups and Tx path fixes, Peter Crosthwaite, 2014/01/01
- [Qemu-devel] [PATCH target-arm v2 01/11] char/cadence_uart: Mark struct fields as public/private, Peter Crosthwaite, 2014/01/01
- [Qemu-devel] [PATCH target-arm v2 02/11] char/cadence_uart: Add missing uart_update_state, Peter Crosthwaite, 2014/01/01
- [Qemu-devel] [PATCH target-arm v2 03/11] char/cadence_uart: Fix reset., Peter Crosthwaite, 2014/01/01
- [Qemu-devel] [PATCH target-arm v2 04/11] char/cadence_uart: s/r_fifo/rx_fifo, Peter Crosthwaite, 2014/01/01
- [Qemu-devel] [PATCH target-arm v2 05/11] char/cadence_uart: Simplify status generation, Peter Crosthwaite, 2014/01/01
- [Qemu-devel] [PATCH target-arm v2 06/11] char/cadence_uart: Define Missing SR/ISR fields, Peter Crosthwaite, 2014/01/01
- [Qemu-devel] [PATCH target-arm v2 07/11] char/cadence_uart: Remove TX timer & add TX FIFO state, Peter Crosthwaite, 2014/01/01
- [Qemu-devel] [PATCH target-arm v2 08/11] char/cadence_uart: Fix can_receive logic, Peter Crosthwaite, 2014/01/01
- [Qemu-devel] [PATCH target-arm v2 09/11] char/cadence_uart: Use the TX fifo for transmission,
Peter Crosthwaite <=
- [Qemu-devel] [PATCH target-arm v2 10/11] char/cadence_uart: Delete redundant rx rst logic, Peter Crosthwaite, 2014/01/01
- [Qemu-devel] [PATCH target-arm v2 11/11] char/cadence_uart: Implement Tx flow control, Peter Crosthwaite, 2014/01/01
- Re: [Qemu-devel] [PATCH target-arm v2 00/11] Cadence UART cleanups and Tx path fixes, Peter Maydell, 2014/01/06