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[Qemu-devel] [PULL 61/76] softfloat: Fix float64_to_uint64_round_to_zero
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 61/76] softfloat: Fix float64_to_uint64_round_to_zero |
Date: |
Tue, 7 Jan 2014 20:03:57 +0000 |
From: Tom Musta <address@hidden>
The float64_to_uint64_round_to_zero routine is incorrect.
For example, the following test pattern:
46697351FF4AEC29 / 0x1.97351ff4aec29p+103
currently produces 8000000000000000 instead of FFFFFFFFFFFFFFFF.
This patch re-implements the routine to temporarily force the
rounding mode and use the float64_to_uint64 routine.
This contribution can be licensed under either the softfloat-2a or -2b
license.
Signed-off-by: Tom Musta <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
fpu/softfloat.c | 12 +++++-------
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index c2c1a56..f782c24 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -6792,13 +6792,11 @@ uint64_t float64_to_uint64(float64 a STATUS_PARAM)
uint64_t float64_to_uint64_round_to_zero (float64 a STATUS_PARAM)
{
- int64_t v;
-
- v = float64_val(int64_to_float64(INT64_MIN STATUS_VAR));
- v += float64_val(a);
- v = float64_to_int64_round_to_zero(make_float64(v) STATUS_VAR);
-
- return v - INT64_MIN;
+ signed char current_rounding_mode = STATUS(float_rounding_mode);
+ set_float_rounding_mode(float_round_to_zero STATUS_VAR);
+ int64_t v = float64_to_uint64(a STATUS_VAR);
+ set_float_rounding_mode(current_rounding_mode STATUS_VAR);
+ return v;
}
#define COMPARE(s, nan_exp) \
--
1.8.5
- [Qemu-devel] [PULL 75/76] target-arm: A64: Add 1-source 32-to-32 and 64-to-64 FP instructions, (continued)
- [Qemu-devel] [PULL 75/76] target-arm: A64: Add 1-source 32-to-32 and 64-to-64 FP instructions, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 18/76] target-arm: A64: add support for conditional compare insns, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 12/76] target-arm: Update generic cpreg code for AArch64, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 11/76] target-arm: Pull "add one cpreg to hashtable" into its own function, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 10/76] target-arm: A64: implement FMOV, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 67/76] softfloat: Refactor code handling various rounding modes, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 71/76] target-arm: Ignore most exceptions from scalbn when doing fixpoint conversion, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 70/76] target-arm: Rename A32 VFP conversion helpers, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 66/76] softfloat: Add float16 <=> float64 conversion functions, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 68/76] softfloat: Add support for ties-away rounding, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 61/76] softfloat: Fix float64_to_uint64_round_to_zero,
Peter Maydell <=
- [Qemu-devel] [PULL 73/76] target-arm: A64: Add floating-point<->fixed-point instructions, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 59/76] softfloat: Fix factor 2 error for scalbn on denormal inputs, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 72/76] target-arm: A64: Add extra VFP fixed point conversion helpers, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 60/76] softfloat: Add float32_to_uint64(), Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 76/76] target-arm: A64: Add support for FCVT between half, single and double, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 51/76] arm_gic: Rename GIC_X_TRIGGER to GIC_X_EDGE_TRIGGER, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 69/76] target-arm: Prepare VFP_CONV_FIX helpers for A64 uses, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 54/76] softfloat: Add float to 16bit integer conversions., Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 49/76] arm/xilinx_zynq: Always instantiate the GEMs, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 62/76] softfloat: Fix float64_to_uint32, Peter Maydell, 2014/01/07