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[Qemu-devel] [PULL 46/76] char/cadence_uart: Implement Tx flow control
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 46/76] char/cadence_uart: Implement Tx flow control |
Date: |
Tue, 7 Jan 2014 20:03:42 +0000 |
From: Peter Crosthwaite <address@hidden>
If the UART back-end blocks, buffer in the Tx FIFO to try again later.
This stops the IO-thread busy waiting on char back-ends (which causes
all sorts of performance problems).
Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
hw/char/cadence_uart.c | 31 +++++++++++++++++++++++++++++--
1 file changed, 29 insertions(+), 2 deletions(-)
diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
index 8a9ef81..1012f1a 100644
--- a/hw/char/cadence_uart.c
+++ b/hw/char/cadence_uart.c
@@ -286,6 +286,34 @@ static void uart_write_rx_fifo(void *opaque, const uint8_t
*buf, int size)
uart_update_status(s);
}
+static gboolean cadence_uart_xmit(GIOChannel *chan, GIOCondition cond,
+ void *opaque)
+{
+ UartState *s = opaque;
+ int ret;
+
+ /* instant drain the fifo when there's no back-end */
+ if (!s->chr) {
+ s->tx_count = 0;
+ }
+
+ if (!s->tx_count) {
+ return FALSE;
+ }
+
+ ret = qemu_chr_fe_write(s->chr, s->tx_fifo, s->tx_count);
+ s->tx_count -= ret;
+ memmove(s->tx_fifo, s->tx_fifo + ret, s->tx_count);
+
+ if (s->tx_count) {
+ int r = qemu_chr_fe_add_watch(s->chr, G_IO_OUT, cadence_uart_xmit, s);
+ assert(r);
+ }
+
+ uart_update_status(s);
+ return FALSE;
+}
+
static void uart_write_tx_fifo(UartState *s, const uint8_t *buf, int size)
{
if ((s->r[R_CR] & UART_CR_TX_DIS) || !(s->r[R_CR] & UART_CR_TX_EN)) {
@@ -306,8 +334,7 @@ static void uart_write_tx_fifo(UartState *s, const uint8_t
*buf, int size)
memcpy(s->tx_fifo + s->tx_count, buf, size);
s->tx_count += size;
- qemu_chr_fe_write_all(s->chr, s->tx_fifo, s->tx_count);
- s->tx_count = 0;
+ cadence_uart_xmit(NULL, G_IO_OUT, s);
}
static void uart_receive(void *opaque, const uint8_t *buf, int size)
--
1.8.5
- [Qemu-devel] [PULL 38/76] char/cadence_uart: Fix reset., (continued)
- [Qemu-devel] [PULL 38/76] char/cadence_uart: Fix reset., Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 24/76] .travis.yml: Add aarch64-* targets, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 27/76] target-arm: A64: Fix vector register access on bigendian hosts, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 50/76] target-arm: fix build with gcc 4.8.2, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 39/76] char/cadence_uart: s/r_fifo/rx_fifo, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 31/76] target-arm: A64: Add fmov (scalar, immediate) instruction, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 58/76] softfloat: Only raise Invalid when conversions to int are out of range, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 29/76] target-arm: A64: Add "Floating-point data-processing (2 source)" insns, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 40/76] char/cadence_uart: Simplify status generation, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 09/76] target-arm: A64: Add decoder skeleton for FP instructions, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 46/76] char/cadence_uart: Implement Tx flow control,
Peter Maydell <=
- [Qemu-devel] [PULL 45/76] char/cadence_uart: Delete redundant rx rst logic, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 42/76] char/cadence_uart: Remove TX timer & add TX FIFO state, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 41/76] char/cadence_uart: Define Missing SR/ISR fields, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 55/76] softfloat: Add 16 bit integer to float conversions, Peter Maydell, 2014/01/07