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[Qemu-devel] [V6 PATCH 16/18] target-ppc: Floating Merge Word Instructio
From: |
Tom Musta |
Subject: |
[Qemu-devel] [V6 PATCH 16/18] target-ppc: Floating Merge Word Instructions |
Date: |
Fri, 10 Jan 2014 13:08:00 -0600 |
This patch adds the Floating Merge Even Word (fmrgew) and Floating
Merge Odd Word (fmrgow) instructions.
Signed-off-by: Tom Musta <address@hidden>
---
V6: New.
target-ppc/translate.c | 31 +++++++++++++++++++++++++++++++
1 files changed, 31 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index ec945a2..7f2a66f 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -2294,6 +2294,35 @@ static void gen_fcpsgn(DisasContext *ctx)
gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
}
+static void gen_fmrgew(DisasContext *ctx)
+{
+ TCGv_i64 b0;
+ if (unlikely(!ctx->fpu_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_FPU);
+ return;
+ }
+ b0 = tcg_temp_new_i64();
+ tcg_gen_shri_i64(b0, cpu_fpr[rB(ctx->opcode)], 32);
+ tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
+ b0, 0, 32);
+ tcg_temp_free_i64(b0);
+}
+
+static void gen_fmrgow(DisasContext *ctx)
+{
+ TCGv_i64 a1;
+ if (unlikely(!ctx->fpu_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_FPU);
+ return;
+ }
+ a1 = tcg_temp_new_i64();
+ tcg_gen_shli_i64(a1, cpu_fpr[rA(ctx->opcode)], 32);
+ tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)],
+ a1, cpu_fpr[rB(ctx->opcode)],
+ 0, 32);
+ tcg_temp_free_i64(a1);
+}
+
/*** Floating-Point status & ctrl register ***/
/* mcrfs */
@@ -9397,6 +9426,8 @@ GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT),
GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT),
GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205),
+GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE, PPC2_VSX207),
+GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207),
GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
--
1.7.1
- [Qemu-devel] [V6 PATCH 06/18] target-ppc: VSX Stage 4: Add xsaddsp and xssubsp, (continued)
- [Qemu-devel] [V6 PATCH 06/18] target-ppc: VSX Stage 4: Add xsaddsp and xssubsp, Tom Musta, 2014/01/10
- [Qemu-devel] [V6 PATCH 07/18] target-ppc: VSX Stage 4: Add xsmulsp, Tom Musta, 2014/01/10
- [Qemu-devel] [V6 PATCH 08/18] target-ppc: VSX Stage 4: Add xsdivsp, Tom Musta, 2014/01/10
- [Qemu-devel] [V6 PATCH 09/18] target-ppc: VSX Stage 4: Add xsresp, Tom Musta, 2014/01/10
- [Qemu-devel] [V6 PATCH 10/18] target-ppc: VSX Stage 4: Add xssqrtsp, Tom Musta, 2014/01/10
- [Qemu-devel] [V6 PATCH 11/18] target-ppc: VSX Stage 4: add xsrsqrtesp, Tom Musta, 2014/01/10
- [Qemu-devel] [V6 PATCH 15/18] target-ppc: Move To/From VSR Instructions, Tom Musta, 2014/01/10
- [Qemu-devel] [V6 PATCH 16/18] target-ppc: Floating Merge Word Instructions,
Tom Musta <=
- [Qemu-devel] [V6 PATCH 17/18] target-ppc: Scalar Round to Single Precision, Tom Musta, 2014/01/10
- [Qemu-devel] [V6 PATCH 18/18] target-ppc: Scalar Non-Signalling Conversions, Tom Musta, 2014/01/10
- [Qemu-devel] [V6 PATCH 13/18] target-ppc: VSX Stage 4: Add xscvsxdsp and xscvuxdsp, Tom Musta, 2014/01/10
- [Qemu-devel] [V6 PATCH 12/18] target-ppc: VSX Stage 4: Add Scalar SP Fused Multiply-Adds, Tom Musta, 2014/01/10
- [Qemu-devel] [V6 PATCH 14/18] target-ppc: VSX Stage 4: Add xxleqv, xxlnand and xxlorc, Tom Musta, 2014/01/10