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Re: [Qemu-devel] [PATCH 03/24] target-arm: Restrict check_ap() use of S
From: |
Peter Crosthwaite |
Subject: |
Re: [Qemu-devel] [PATCH 03/24] target-arm: Restrict check_ap() use of S and R bits to v6 and earlier |
Date: |
Sat, 25 Jan 2014 09:28:08 +1000 |
On Wed, Jan 22, 2014 at 6:12 AM, Peter Maydell <address@hidden> wrote:
> The SCTLR bits S and R (8 and 9) only exist in ARMv6 and earlier.
> In ARMv7 these bits RAZ, and in ARMv8 they are reassigned. Guard
> the use of them in check_ap() so that we don't get incorrect results
> for ARMv8 CPUs.
>
> Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
> ---
> target-arm/helper.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 792953e..205e36a 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -2765,6 +2765,9 @@ static inline int check_ap(CPUARMState *env, int ap,
> int domain_prot,
>
> switch (ap) {
> case 0:
> + if (arm_feature(env, ARM_FEATURE_V7)) {
> + return 0;
> + }
> if (access_type == 1)
> return 0;
> switch (env->cp15.c1_sys & (SCTLR_S | SCTLR_R)) {
> --
> 1.8.5
>
>
- [Qemu-devel] [PATCH 00/24] target-arm: implement some AArch64 system registers, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 18/24] target-arm: Implement AArch64 VBAR_EL1, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 11/24] target-arm: Implement AArch64 DAIF system register, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 16/24] target-arm: Implement AArch64 SCTLR_EL1, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 10/24] target-arm: Implement AArch64 MIDR_EL1, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 06/24] target-arm: A64: Implement store-exclusive for system mode, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 03/24] target-arm: Restrict check_ap() use of S and R bits to v6 and earlier, Peter Maydell, 2014/01/21
- Re: [Qemu-devel] [PATCH 03/24] target-arm: Restrict check_ap() use of S and R bits to v6 and earlier,
Peter Crosthwaite <=
- [Qemu-devel] [PATCH 12/24] target-arm: Implement AArch64 cache invalidate/clean ops, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 09/24] target-arm: Implement AArch64 CurrentEL sysreg, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 23/24] target-arm: Implement AArch64 dummy breakpoint and watchpoint registers, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 22/24] target-arm: Implement AArch64 ID and feature registers, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 02/24] target-arm: Define names for SCTLR bits, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 08/24] target-arm: A64: Implement MSR (immediate) instructions, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 24/24] target-arm: Implement AArch64 OSLAR_EL1 sysreg as WI, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 20/24] target-arm: Implement AArch64 MPIDR, Peter Maydell, 2014/01/21