Re: [Qemu-devel] [PATCH 18/24] target-arm: Implement AArch64 VBAR_EL1

[Peter Crosthwaite]

On Wed, Jan 22, 2014 at 6:12 AM, Peter Maydell <address@hidden> wrote:
> Implement the A64 view of the VBAR system register.
>
> Signed-off-by: Peter Maydell <address@hidden>

Reviewed-by: Peter Crosthwaite <address@hidden>

> ---
>  target-arm/cpu.h    | 2 +-
>  target-arm/helper.c | 9 ++++++++-
>  2 files changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index a7d6274..6f4d174 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -200,7 +200,7 @@ typedef struct CPUARMState {
>          uint32_t c9_pmuserenr; /* perf monitor user enable */
>          uint32_t c9_pminten; /* perf monitor interrupt enables */
>          uint64_t mair_el1;
> -        uint32_t c12_vbar; /* vector base address register */
> +        uint64_t c12_vbar; /* vector base address register */
>          uint32_t c13_fcse; /* FCSE PID.  */
>          uint32_t c13_context; /* Context ID.  */
>          uint64_t tpidr_el0; /* User RW Thread register.  */
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 5912b13..e2ae159 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -580,6 +580,12 @@ static int pmintenclr_write(CPUARMState *env, const 
> ARMCPRegInfo *ri,
>  static int vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
>                        uint64_t value)
>  {
> +    /* Note that even though the AArch64 view of this register has bits
> +     * [10:0] all RES0 we can only mask the bottom 5, to comply with the
> +     * architectural requirements for bits which are RES0 only in some
> +     * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
> +     * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
> +     */
>      env->cp15.c12_vbar = value & ~0x1Ful;
>      return 0;
>  }
> @@ -669,7 +675,8 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
>        .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
>        .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
>        .resetvalue = 0, .writefn = pmintenclr_write, },
> -    { .name = "VBAR", .cp = 15, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
> +    { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
> +      .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
>        .access = PL1_RW, .writefn = vbar_write,
>        .fieldoffset = offsetof(CPUARMState, cp15.c12_vbar),
>        .resetvalue = 0 },
> --
> 1.8.5
>
>