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[Qemu-devel] [PATCH 04/21] target-arm: A64: Add top level decode for SIM
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 04/21] target-arm: A64: Add top level decode for SIMD 3-same group |
Date: |
Sun, 26 Jan 2014 19:24:55 +0000 |
Add top level decode for the A64 SIMD three regs same group
(C3.6.16), splitting it into the pairwise, logical, float and
integer subgroups.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target-arm/translate-a64.c | 45 ++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 44 insertions(+), 1 deletion(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 6ff3e43..2079c96 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -5948,6 +5948,30 @@ static void disas_simd_three_reg_diff(DisasContext *s,
uint32_t insn)
}
}
+/* Logic op (opcode == 3) subgroup of C3.6.16. */
+static void disas_simd_3same_logic(DisasContext *s, uint32_t insn)
+{
+ unsupported_encoding(s, insn);
+}
+
+/* Pairwise op subgroup of C3.6.16. */
+static void disas_simd_3same_pair(DisasContext *s, uint32_t insn)
+{
+ unsupported_encoding(s, insn);
+}
+
+/* Floating point op subgroup of C3.6.16. */
+static void disas_simd_3same_float(DisasContext *s, uint32_t insn)
+{
+ unsupported_encoding(s, insn);
+}
+
+/* Integer op subgroup of C3.6.16. */
+static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
+{
+ unsupported_encoding(s, insn);
+}
+
/* C3.6.16 AdvSIMD three same
* 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
* +---+---+---+-----------+------+---+------+--------+---+------+------+
@@ -5956,7 +5980,26 @@ static void disas_simd_three_reg_diff(DisasContext *s,
uint32_t insn)
*/
static void disas_simd_three_reg_same(DisasContext *s, uint32_t insn)
{
- unsupported_encoding(s, insn);
+ int opcode = extract32(insn, 11, 5);
+
+ switch (opcode) {
+ case 0x3: /* logic ops */
+ disas_simd_3same_logic(s, insn);
+ break;
+ case 0x17: /* ADDP */
+ case 0x14: /* SMAXP, UMAXP */
+ case 0x15: /* SMINP, UMINP */
+ /* Pairwise operations */
+ disas_simd_3same_pair(s, insn);
+ break;
+ case 0x18 ... 0x31:
+ /* floating point ops, sz[1] and U are part of opcode */
+ disas_simd_3same_float(s, insn);
+ break;
+ default:
+ disas_simd_3same_int(s, insn);
+ break;
+ }
}
/* C3.6.17 AdvSIMD two reg misc
--
1.8.5
- Re: [Qemu-devel] [PATCH 10/21] target-arm: A64: Implement remaining non-pairwise int SIMD 3-reg-same insns, (continued)
- [Qemu-devel] [PATCH 01/21] target-arm: A64: Add SIMD three-different multiply accumulate insns, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 21/21] target-arm: A64: Add FNEG and FABS to the SIMD 2-reg-misc group, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 11/21] target-arm: A64: Implement pairwise integer ops from 3-reg-same SIMD, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 02/21] target-arm: A64: Add SIMD three-different ABDL instructions, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 05/21] target-arm: A64: Add logic ops from SIMD 3 same group, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 14/21] target-arm: A64: Implement remaining integer scalar-3-same insns, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 03/21] target-arm: A64: Add SIMD scalar 3 same add, sub and compare ops, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 04/21] target-arm: A64: Add top level decode for SIMD 3-same group,
Peter Maydell <=
- [Qemu-devel] [PATCH 07/21] target-arm: A64: Add simple SIMD 3-same floating point ops, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 09/21] target-arm: A64: Implement SIMD 3-reg-same shift and saturate insns, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 06/21] target-arm: A64: Add integer ops from SIMD 3-same group, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 08/21] target-arm: A64: Add SIMD shift by immediate, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 12/21] tcg: Add TCGV_UNUSED_PTR, TCGV_IS_UNUSED_PTR, TCGV_EQUAL_PTR, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 15/21] target-arm: A64: Add SIMD simple 64 bit insns from scalar 2-reg misc, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 13/21] target-arm: A64: Implement scalar pairwise ops, Peter Maydell, 2014/01/26