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[Qemu-devel] [PULL 28/38] target-arm: A64: Add top level decode for SIMD
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 28/38] target-arm: A64: Add top level decode for SIMD 3-same group |
Date: |
Wed, 29 Jan 2014 13:39:55 +0000 |
Add top level decode for the A64 SIMD three regs same group
(C3.6.16), splitting it into the pairwise, logical, float and
integer subgroups.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target-arm/translate-a64.c | 45 ++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 44 insertions(+), 1 deletion(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index f0ebbb5..a215f083 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -5920,6 +5920,30 @@ static void disas_simd_three_reg_diff(DisasContext *s,
uint32_t insn)
}
}
+/* Logic op (opcode == 3) subgroup of C3.6.16. */
+static void disas_simd_3same_logic(DisasContext *s, uint32_t insn)
+{
+ unsupported_encoding(s, insn);
+}
+
+/* Pairwise op subgroup of C3.6.16. */
+static void disas_simd_3same_pair(DisasContext *s, uint32_t insn)
+{
+ unsupported_encoding(s, insn);
+}
+
+/* Floating point op subgroup of C3.6.16. */
+static void disas_simd_3same_float(DisasContext *s, uint32_t insn)
+{
+ unsupported_encoding(s, insn);
+}
+
+/* Integer op subgroup of C3.6.16. */
+static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
+{
+ unsupported_encoding(s, insn);
+}
+
/* C3.6.16 AdvSIMD three same
* 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
* +---+---+---+-----------+------+---+------+--------+---+------+------+
@@ -5928,7 +5952,26 @@ static void disas_simd_three_reg_diff(DisasContext *s,
uint32_t insn)
*/
static void disas_simd_three_reg_same(DisasContext *s, uint32_t insn)
{
- unsupported_encoding(s, insn);
+ int opcode = extract32(insn, 11, 5);
+
+ switch (opcode) {
+ case 0x3: /* logic ops */
+ disas_simd_3same_logic(s, insn);
+ break;
+ case 0x17: /* ADDP */
+ case 0x14: /* SMAXP, UMAXP */
+ case 0x15: /* SMINP, UMINP */
+ /* Pairwise operations */
+ disas_simd_3same_pair(s, insn);
+ break;
+ case 0x18 ... 0x31:
+ /* floating point ops, sz[1] and U are part of opcode */
+ disas_simd_3same_float(s, insn);
+ break;
+ default:
+ disas_simd_3same_int(s, insn);
+ break;
+ }
}
/* C3.6.17 AdvSIMD two reg misc
--
1.8.5
- [Qemu-devel] [PULL 33/38] linux-headers: Update from Linus' master ba635f8, (continued)
- [Qemu-devel] [PULL 33/38] linux-headers: Update from Linus' master ba635f8, Peter Maydell, 2014/01/29
- [Qemu-devel] [PULL 09/38] target-arm: A64: Add SIMD modified immediate group, Peter Maydell, 2014/01/29
- [Qemu-devel] [PULL 34/38] kvm: Introduce kvm_arch_irqchip_create, Peter Maydell, 2014/01/29
- [Qemu-devel] [PULL 32/38] target-arm: A64: Add SIMD shift by immediate, Peter Maydell, 2014/01/29
- [Qemu-devel] [PULL 24/38] target-arm: Add AArch32 SIMD VCVTA, VCVTN, VCVTP and VCVTM, Peter Maydell, 2014/01/29
- [Qemu-devel] [PULL 27/38] target-arm: A64: Add SIMD scalar 3 same add, sub and compare ops, Peter Maydell, 2014/01/29
- [Qemu-devel] [PULL 17/38] target-arm: Add support for AArch32 FP VRINTR, Peter Maydell, 2014/01/29
- [Qemu-devel] [PULL 31/38] target-arm: A64: Add simple SIMD 3-same floating point ops, Peter Maydell, 2014/01/29
- [Qemu-devel] [PULL 29/38] target-arm: A64: Add logic ops from SIMD 3 same group, Peter Maydell, 2014/01/29
- [Qemu-devel] [PULL 30/38] target-arm: A64: Add integer ops from SIMD 3-same group, Peter Maydell, 2014/01/29
- [Qemu-devel] [PULL 28/38] target-arm: A64: Add top level decode for SIMD 3-same group,
Peter Maydell <=
- [Qemu-devel] [PULL 18/38] target-arm: Add support for AArch32 FP VRINTZ, Peter Maydell, 2014/01/29
- [Qemu-devel] [PULL 01/38] target-arm: A64: Add SIMD ld/st multiple, Peter Maydell, 2014/01/29
- [Qemu-devel] [PULL 14/38] display: avoid multi-statement macro, Peter Maydell, 2014/01/29
- [Qemu-devel] [PULL 13/38] ZYNQ: Implement board MIDR control for Zynq, Peter Maydell, 2014/01/29
- [Qemu-devel] [PULL 19/38] target-arm: Add support for AArch32 FP VRINTX, Peter Maydell, 2014/01/29
- [Qemu-devel] [PULL 21/38] target-arm: Add set_neon_rmode helper, Peter Maydell, 2014/01/29
- [Qemu-devel] [PULL 26/38] target-arm: A64: Add SIMD three-different ABDL instructions, Peter Maydell, 2014/01/29
- [Qemu-devel] [PULL 07/38] target-arm: A64: Add SIMD across-lanes instructions, Peter Maydell, 2014/01/29
- [Qemu-devel] [PULL 15/38] target-arm: Move arm_rmode_to_sf to a shared location., Peter Maydell, 2014/01/29
- [Qemu-devel] [PULL 05/38] target-arm: A64: Add SIMD TBL/TBLX, Peter Maydell, 2014/01/29