Re: [Qemu-devel] [PATCH target-arm v4 1/1] target-arm: Implements the ARM PMCCNTR register

[Peter Crosthwaite]

On Thu, Jan 30, 2014 at 8:22 PM, Peter Maydell <address@hidden> wrote:
> On 30 January 2014 07:00, Peter Crosthwaite
> <address@hidden> wrote:
>> On Wed, Jan 29, 2014 at 10:28 PM, Peter Maydell
>> <address@hidden> wrote:
>>> This will break migration. You must provide a mechanism for the
>>> migration to do a "read register on source end; write value to register
>>> at destination". (You also in this case need to make sure migration
>>> works whether the migration process writes the control register
>>> first and the counter second or the other way around.)
>>>
>>
>> Is this as simple as hooking up the default raw_write/raw_read
>> handlers? From a migration perspective is should be a case of simply
>> saving and loading the state value with no fancyness. The vm timer
>> should migrate so there should be no need for any of the syncing
>> effects on either end of a migration.
>
> You also have to consider KVM<->TCG migration, so the value on
> the wire should be the actual value of the register, not the
> value of TCG's underlying state. So you need a raw read/write
> fn (and also to fix up the one for the enable register) but it's
> not as simple as just using the raw_read/write functions.
>

At the point, you're better off just implementing the actual write
functionality, considering the semantic of the write exactly matches a
"raw write" - i.e. update the register value. Once the the proper
write fn is implement these migration concerns will just come out in
the wash.

Regards,
Peter

> thanks
> -- PMM
>