[Qemu-devel] [PULL v2 00/34] target-arm queue

[Peter Maydell]

v2 of target-arm queue, with the KVM irqchip creation patchset dropped;
since the other 34 patches are unchanged I'm not retransmitting them.
Please pull.

thanks
-- PMM

The following changes since commit 89e4a51ca9546a7bbe1998c4e3d4a3ac3a0c19be:

  Merge remote-tracking branch 'stefanha/tags/tracing-pull-request' into 
staging (2014-01-31 11:13:08 +0000)

are available in the git repository at:


  git://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20140131

for you to fetch changes up to 5b0adce156216fb24dcc5f1683e8b686f3793fff:

  arm_gic: Fix GICD_ICPENDR and GICD_ISPENDR writes (2014-01-31 14:47:38 +0000)

----------------------------------------------------------------
target-arm queue:
 * implementation of first part of the A64 Neon instruction set
 * v8 AArch32 rounding and 16<->64 fp conversion instructions
 * fix MIDR value on Zynq boards
 * some minor bugfixes/code cleanups

----------------------------------------------------------------
Alex Bennée (5):
      target-arm: A64: Add SIMD ld/st multiple
      target-arm: A64: Add decode skeleton for SIMD data processing insns
      target-arm: A64: Add SIMD copy operations
      target-arm: A64: Add SIMD modified immediate group
      target-arm: A64: Add SIMD shift by immediate

Alistair Francis (2):
      ARM: Convert MIDR to a property
      ZYNQ: Implement board MIDR control for Zynq

Christoffer Dall (2):
      arm_gic: Introduce define for GIC_NR_SGIS
      arm_gic: Fix GICD_ICPENDR and GICD_ISPENDR writes

Michael Matz (3):
      target-arm: A64: Add SIMD TBL/TBLX
      target-arm: A64: Add SIMD ZIP/UZP/TRN
      target-arm: A64: Add SIMD across-lanes instructions

Paolo Bonzini (1):
      display: avoid multi-statement macro

Peter Maydell (11):
      target-arm: A64: Add SIMD ld/st single
      target-arm: A64: Add SIMD EXT
      target-arm: A64: Add SIMD scalar copy instructions
      hw/arm/boot: Don't set up ATAGS for autogenerated dtb booting
      target-arm: A64: Add SIMD three-different multiply accumulate insns
      target-arm: A64: Add SIMD three-different ABDL instructions
      target-arm: A64: Add SIMD scalar 3 same add, sub and compare ops
      target-arm: A64: Add top level decode for SIMD 3-same group
      target-arm: A64: Add logic ops from SIMD 3 same group
      target-arm: A64: Add integer ops from SIMD 3-same group
      target-arm: A64: Add simple SIMD 3-same floating point ops

Will Newton (10):
      target-arm: Move arm_rmode_to_sf to a shared location.
      target-arm: Add AArch32 FP VRINTA, VRINTN, VRINTP and VRINTM
      target-arm: Add support for AArch32 FP VRINTR
      target-arm: Add support for AArch32 FP VRINTZ
      target-arm: Add support for AArch32 FP VRINTX
      target-arm: Add support for AArch32 SIMD VRINTX
      target-arm: Add set_neon_rmode helper
      target-arm: Add AArch32 SIMD VRINTA, VRINTN, VRINTP, VRINTM, VRINTZ
      target-arm: Add AArch32 FP VCVTA, VCVTN, VCVTP and VCVTM
      target-arm: Add AArch32 SIMD VCVTA, VCVTN, VCVTP and VCVTM

 hw/arm/boot.c                    |    9 +-
 hw/arm/xilinx_zynq.c             |    7 +
 hw/display/blizzard_template.h   |   40 +-
 hw/display/pl110_template.h      |   12 +-
 hw/display/pxa2xx_template.h     |   22 +-
 hw/display/tc6393xb_template.h   |   14 +-
 hw/intc/arm_gic.c                |   21 +-
 include/hw/intc/arm_gic_common.h |    1 +
 target-arm/cpu.c                 |    1 +
 target-arm/cpu.h                 |    2 +
 target-arm/helper-a64.c          |   31 +
 target-arm/helper-a64.h          |    1 +
 target-arm/helper.c              |   45 +
 target-arm/helper.h              |    1 +
 target-arm/translate-a64.c       | 2707 +++++++++++++++++++++++++++++++++++++-
 target-arm/translate.c           |  251 ++++
 16 files changed, 3091 insertions(+), 74 deletions(-)