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[Qemu-devel] [PATCH v2 07/35] target-arm: Add exception level to the AAr
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH v2 07/35] target-arm: Add exception level to the AArch64 TB flags |
Date: |
Fri, 31 Jan 2014 15:45:15 +0000 |
We already implicitly rely on the exception level being
part of the TB flags for coprocessor access, so actually
include it. (This makes no difference for linux-user mode,
which is always in EL0, but will be needed for correct
operation in system emulation.)
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/cpu.h | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 70cd5a0..385cfcd 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -1056,7 +1056,9 @@ static inline int cpu_mmu_index (CPUARMState *env)
#define ARM_TBFLAG_BSWAP_CODE_SHIFT 16
#define ARM_TBFLAG_BSWAP_CODE_MASK (1 << ARM_TBFLAG_BSWAP_CODE_SHIFT)
-/* Bit usage when in AArch64 state: currently no bits defined */
+/* Bit usage when in AArch64 state */
+#define ARM_TBFLAG_AA64_EL_SHIFT 0
+#define ARM_TBFLAG_AA64_EL_MASK (0x3 << ARM_TBFLAG_AA64_EL_SHIFT)
/* some convenience accessor macros */
#define ARM_TBFLAG_AARCH64_STATE(F) \
@@ -1075,13 +1077,16 @@ static inline int cpu_mmu_index (CPUARMState *env)
(((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT)
#define ARM_TBFLAG_BSWAP_CODE(F) \
(((F) & ARM_TBFLAG_BSWAP_CODE_MASK) >> ARM_TBFLAG_BSWAP_CODE_SHIFT)
+#define ARM_TBFLAG_AA64_EL(F) \
+ (((F) & ARM_TBFLAG_AA64_EL_MASK) >> ARM_TBFLAG_AA64_EL_SHIFT)
static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
target_ulong *cs_base, int *flags)
{
if (is_a64(env)) {
*pc = env->pc;
- *flags = ARM_TBFLAG_AARCH64_STATE_MASK;
+ *flags = ARM_TBFLAG_AARCH64_STATE_MASK
+ | arm_current_pl(env) << ARM_TBFLAG_AA64_EL_SHIFT;
} else {
int privmode;
*pc = env->regs[15];
--
1.8.5
- [Qemu-devel] [PATCH v2 00/35] AArch64 system mode: system register rework, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 07/35] target-arm: Add exception level to the AArch64 TB flags,
Peter Maydell <=
- [Qemu-devel] [PATCH v2 10/35] target-arm: Stop underdecoding ARM946 PRBS registers, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 03/35] target-arm: Define names for SCTLR bits, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 23/35] target-arm: Implement AArch64 cache invalidate/clean ops, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 21/35] target-arm: Implement AArch64 MIDR_EL1, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 25/35] target-arm: Implement AArch64 dummy MDSCR_EL1, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 24/35] target-arm: Implement AArch64 TLB invalidate ops, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 05/35] target-arm: Remove unused ARMCPUState sr substruct, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 14/35] target-arm: Convert miscellaneous reginfo structs to accessfn, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 31/35] target-arm: Implement AArch64 MPIDR, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 27/35] target-arm: Implement AArch64 SCTLR_EL1, Peter Maydell, 2014/01/31