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[Qemu-devel] [PATCH v2 35/35] target-arm: Implement AArch64 OSLAR_EL1 sy
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH v2 35/35] target-arm: Implement AArch64 OSLAR_EL1 sysreg as WI |
Date: |
Fri, 31 Jan 2014 15:45:43 +0000 |
Define a dummy version of the AArch64 OSLAR_EL1 system register
which just ignores writes. Linux will always write to this (it
is the OS lock used for debugging), but we don't support debug.
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/helper.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 1621030..43a4f31 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1764,6 +1764,10 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
{ .name = "MDSCR_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ /* We define a dummy WI OSLAR_EL1, because Linux writes to it. */
+ { .name = "OSLAR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
+ .access = PL1_W, .type = ARM_CP_NOP },
REGINFO_SENTINEL
};
--
1.8.5
- [Qemu-devel] [PATCH v2 18/35] target-arm: Fix incorrect type for value argument to write_raw_cp_reg, (continued)
- [Qemu-devel] [PATCH v2 18/35] target-arm: Fix incorrect type for value argument to write_raw_cp_reg, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 19/35] target-arm: A64: Make cache ID registers visible to AArch64, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 17/35] target-arm: Remove failure status return from read/write_raw_cp_reg, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 04/35] target-arm: Restrict check_ap() use of S and R bits to v6 and earlier, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 26/35] target-arm: Implement AArch64 memory attribute registers, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 09/35] target-arm: A64: Implement MSR (immediate) instructions, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 02/35] target-arm/kvm-consts.h: Define QEMU constants for known KVM CPUs, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 34/35] target-arm: Implement AArch64 dummy breakpoint and watchpoint registers, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 15/35] target-arm: Drop success/fail return from cpreg read and write functions, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 32/35] target-arm: Implement AArch64 generic timers, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 35/35] target-arm: Implement AArch64 OSLAR_EL1 sysreg as WI,
Peter Maydell <=
- [Qemu-devel] [PATCH v2 01/35] target-arm: Fix raw read and write functions on AArch64 registers, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 30/35] target-arm: Implement AArch64 TTBR*, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 08/35] target-arm: A64: Implement store-exclusive for system mode, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 28/35] target-arm: Implement AArch64 TCR_EL1, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 11/35] target-arm: Split cpreg access checks out from read/write functions, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 22/35] target-arm: Implement AArch64 DAIF system register, Peter Maydell, 2014/01/31