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[Qemu-devel] [PULL 19/29] arm_gic: Add GICC_APRn state to the GICState
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 19/29] arm_gic: Add GICC_APRn state to the GICState |
Date: |
Sat, 8 Feb 2014 15:57:54 +0000 |
From: Christoffer Dall <address@hidden>
The GICC_APRn registers are not currently supported by the ARM GIC v2.0
emulation. This patch adds the missing state.
Note that we also change the number of APRs to use a define GIC_NR_APRS
based on the maximum number of preemption levels. This patch also adds
RAZ/WI accessors for the four registers on the emulated CPU interface.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Christoffer Dall <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
hw/intc/arm_gic.c | 5 +++++
hw/intc/arm_gic_common.c | 5 +++--
include/hw/intc/arm_gic_common.h | 19 +++++++++++++++++++
3 files changed, 27 insertions(+), 2 deletions(-)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 5413a24..93eaa6b 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -678,6 +678,8 @@ static uint32_t gic_cpu_read(GICState *s, int cpu, int
offset)
return s->current_pending[cpu];
case 0x1c: /* Aliased Binary Point */
return s->abpr[cpu];
+ case 0xd0: case 0xd4: case 0xd8: case 0xdc:
+ return s->apr[(offset - 0xd0) / 4][cpu];
default:
qemu_log_mask(LOG_GUEST_ERROR,
"gic_cpu_read: Bad offset %x\n", (int)offset);
@@ -705,6 +707,9 @@ static void gic_cpu_write(GICState *s, int cpu, int offset,
uint32_t value)
s->abpr[cpu] = (value & 0x7);
}
break;
+ case 0xd0: case 0xd4: case 0xd8: case 0xdc:
+ qemu_log_mask(LOG_UNIMP, "Writing APR not implemented\n");
+ break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"gic_cpu_write: Bad offset %x\n", (int)offset);
diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c
index d2d8ce1..6d884ec 100644
--- a/hw/intc/arm_gic_common.c
+++ b/hw/intc/arm_gic_common.c
@@ -58,8 +58,8 @@ static const VMStateDescription vmstate_gic_irq_state = {
static const VMStateDescription vmstate_gic = {
.name = "arm_gic",
- .version_id = 6,
- .minimum_version_id = 6,
+ .version_id = 7,
+ .minimum_version_id = 7,
.pre_save = gic_pre_save,
.post_load = gic_post_load,
.fields = (VMStateField[]) {
@@ -78,6 +78,7 @@ static const VMStateDescription vmstate_gic = {
VMSTATE_UINT16_ARRAY(current_pending, GICState, GIC_NCPU),
VMSTATE_UINT8_ARRAY(bpr, GICState, GIC_NCPU),
VMSTATE_UINT8_ARRAY(abpr, GICState, GIC_NCPU),
+ VMSTATE_UINT32_2DARRAY(apr, GICState, GIC_NR_APRS, GIC_NCPU),
VMSTATE_END_OF_LIST()
}
};
diff --git a/include/hw/intc/arm_gic_common.h b/include/hw/intc/arm_gic_common.h
index 983c3cf..89384c2 100644
--- a/include/hw/intc/arm_gic_common.h
+++ b/include/hw/intc/arm_gic_common.h
@@ -31,6 +31,9 @@
/* Maximum number of possible CPU interfaces, determined by GIC architecture */
#define GIC_NCPU 8
+#define MAX_NR_GROUP_PRIO 128
+#define GIC_NR_APRS (MAX_NR_GROUP_PRIO / 32)
+
typedef struct gic_irq_state {
/* The enable bits are only banked for per-cpu interrupts. */
uint8_t enabled;
@@ -75,6 +78,22 @@ typedef struct GICState {
uint8_t bpr[GIC_NCPU];
uint8_t abpr[GIC_NCPU];
+ /* The APR is implementation defined, so we choose a layout identical to
+ * the KVM ABI layout for QEMU's implementation of the gic:
+ * If an interrupt for preemption level X is active, then
+ * APRn[X mod 32] == 0b1, where n = X / 32
+ * otherwise the bit is clear.
+ *
+ * TODO: rewrite the interrupt acknowlege/complete routines to use
+ * the APR registers to track the necessary information to update
+ * s->running_priority[] on interrupt completion (ie completely remove
+ * last_active[][] and running_irq[]). This will be necessary if we ever
+ * want to support TCG<->KVM migration, or TCG guests which can
+ * do power management involving powering down and restarting
+ * the GIC.
+ */
+ uint32_t apr[GIC_NR_APRS][GIC_NCPU];
+
uint32_t num_cpu;
MemoryRegion iomem; /* Distributor */
--
1.8.5
- [Qemu-devel] [PULL 00/29] target-arm queue, Peter Maydell, 2014/02/08
- [Qemu-devel] [PULL 12/29] target-arm: A64: Add 2-reg-misc REV* instructions, Peter Maydell, 2014/02/08
- [Qemu-devel] [PULL 11/29] target-arm: A64: Add narrowing 2-reg-misc instructions, Peter Maydell, 2014/02/08
- [Qemu-devel] [PULL 25/29] util/fifo8: implement push/pop of multiple bytes, Peter Maydell, 2014/02/08
- [Qemu-devel] [PULL 10/29] target-arm: A64: Implement 2-reg-misc CNT, NOT and RBIT, Peter Maydell, 2014/02/08
- [Qemu-devel] [PULL 29/29] arm/zynq: Add software system reset via SCLR, Peter Maydell, 2014/02/08
- [Qemu-devel] [PULL 16/29] arm_gic: Keep track of SGI sources, Peter Maydell, 2014/02/08
- [Qemu-devel] [PULL 01/29] target-arm: A64: Implement SIMD 3-reg-same shift and saturate insns, Peter Maydell, 2014/02/08
- [Qemu-devel] [PULL 06/29] target-arm: A64: Implement remaining integer scalar-3-same insns, Peter Maydell, 2014/02/08
- [Qemu-devel] [PULL 07/29] target-arm: A64: Add SIMD simple 64 bit insns from scalar 2-reg misc, Peter Maydell, 2014/02/08
- [Qemu-devel] [PULL 19/29] arm_gic: Add GICC_APRn state to the GICState,
Peter Maydell <=
- [Qemu-devel] [PULL 28/29] hw/arm/allwinner-a10: initialize EMAC, Peter Maydell, 2014/02/08
- [Qemu-devel] [PULL 05/29] target-arm: A64: Implement scalar pairwise ops, Peter Maydell, 2014/02/08
- [Qemu-devel] [PULL 17/29] arm_gic: Support setting/getting binary point reg, Peter Maydell, 2014/02/08
- [Qemu-devel] [PULL 26/29] util/fifo8: clear fifo head upon reset, Peter Maydell, 2014/02/08
- [Qemu-devel] [PULL 23/29] disas/libvixl: Fix upstream libvixl compilation issues, Peter Maydell, 2014/02/08
- [Qemu-devel] [PULL 09/29] target-arm: A64: Implement 2-register misc compares, ABS, NEG, Peter Maydell, 2014/02/08
- [Qemu-devel] [PULL 21/29] rules.mak: Link with C++ if we have a C++ compiler, Peter Maydell, 2014/02/08
- [Qemu-devel] [PULL 13/29] target-arm: A64: Add FNEG and FABS to the SIMD 2-reg-misc group, Peter Maydell, 2014/02/08
- [Qemu-devel] [PULL 08/29] target-arm: A64: Add skeleton decode for SIMD 2-reg misc group, Peter Maydell, 2014/02/08
- [Qemu-devel] [PULL 02/29] target-arm: A64: Implement remaining non-pairwise int SIMD 3-reg-same insns, Peter Maydell, 2014/02/08