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[Qemu-devel] [PATCH v3 18/31] target-arm: Get MMU index information corr
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH v3 18/31] target-arm: Get MMU index information correct for A64 code |
Date: |
Sat, 15 Feb 2014 16:07:11 +0000 |
Emit the correct MMU index information for loads and stores from
A64 code, rather than hardwiring it to "always kernel mode",
by storing the exception level in the TB flags, and make
cpu_mmu_index() return the right answer when the CPU is in
AArch64 mode.
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/cpu.h | 11 ++++++++---
target-arm/translate-a64.c | 2 +-
2 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index db74ab7..ec0214d 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -1057,7 +1057,7 @@ static inline CPUARMState *cpu_init(const char *cpu_model)
#define MMU_USER_IDX 1
static inline int cpu_mmu_index (CPUARMState *env)
{
- return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0;
+ return arm_current_pl(env) ? 0 : 1;
}
#include "exec/cpu-all.h"
@@ -1084,7 +1084,9 @@ static inline int cpu_mmu_index (CPUARMState *env)
#define ARM_TBFLAG_BSWAP_CODE_SHIFT 16
#define ARM_TBFLAG_BSWAP_CODE_MASK (1 << ARM_TBFLAG_BSWAP_CODE_SHIFT)
-/* Bit usage when in AArch64 state: currently no bits defined */
+/* Bit usage when in AArch64 state */
+#define ARM_TBFLAG_AA64_EL_SHIFT 0
+#define ARM_TBFLAG_AA64_EL_MASK (0x3 << ARM_TBFLAG_AA64_EL_SHIFT)
/* some convenience accessor macros */
#define ARM_TBFLAG_AARCH64_STATE(F) \
@@ -1103,13 +1105,16 @@ static inline int cpu_mmu_index (CPUARMState *env)
(((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT)
#define ARM_TBFLAG_BSWAP_CODE(F) \
(((F) & ARM_TBFLAG_BSWAP_CODE_MASK) >> ARM_TBFLAG_BSWAP_CODE_SHIFT)
+#define ARM_TBFLAG_AA64_EL(F) \
+ (((F) & ARM_TBFLAG_AA64_EL_MASK) >> ARM_TBFLAG_AA64_EL_SHIFT)
static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
target_ulong *cs_base, int *flags)
{
if (is_a64(env)) {
*pc = env->pc;
- *flags = ARM_TBFLAG_AARCH64_STATE_MASK;
+ *flags = ARM_TBFLAG_AARCH64_STATE_MASK
+ | (arm_current_pl(env) << ARM_TBFLAG_AA64_EL_SHIFT);
} else {
int privmode;
*pc = env->regs[15];
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 7c55a90..1714df2 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -8844,7 +8844,7 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu,
dc->condexec_mask = 0;
dc->condexec_cond = 0;
#if !defined(CONFIG_USER_ONLY)
- dc->user = 0;
+ dc->user = (ARM_TBFLAG_AA64_EL(tb->flags) == 0);
#endif
dc->vfp_enabled = 0;
dc->vec_len = 0;
--
1.8.5
- [Qemu-devel] [PATCH v3 05/31] target-arm: Implement AArch64 cache invalidate/clean ops, (continued)
- [Qemu-devel] [PATCH v3 05/31] target-arm: Implement AArch64 cache invalidate/clean ops, Peter Maydell, 2014/02/15
- [Qemu-devel] [PATCH v3 31/31] target-arm: Add v8 mmu translation support, Peter Maydell, 2014/02/15
- [Qemu-devel] [PATCH v3 15/31] target-arm: Implement AArch64 ID and feature registers, Peter Maydell, 2014/02/15
- [Qemu-devel] [PATCH v3 06/31] target-arm: Implement AArch64 TLB invalidate ops, Peter Maydell, 2014/02/15
- [Qemu-devel] [PATCH v3 25/31] target-arm: Define exception record for AArch64 exceptions, Peter Maydell, 2014/02/15
- [Qemu-devel] [PATCH v3 08/31] target-arm: Implement AArch64 memory attribute registers, Peter Maydell, 2014/02/15
- [Qemu-devel] [PATCH v3 27/31] target-arm: Add support for generating exceptions with syndrome information, Peter Maydell, 2014/02/15
- [Qemu-devel] [PATCH v3 26/31] target-arm: Provide correct syndrome information for cpreg access traps, Peter Maydell, 2014/02/15
- [Qemu-devel] [PATCH v3 14/31] target-arm: Implement AArch64 generic timers, Peter Maydell, 2014/02/15
- [Qemu-devel] [PATCH v3 02/31] target-arm: A64: Make cache ID registers visible to AArch64, Peter Maydell, 2014/02/15
- [Qemu-devel] [PATCH v3 18/31] target-arm: Get MMU index information correct for A64 code,
Peter Maydell <=
- [Qemu-devel] [PATCH v3 03/31] target-arm: Implement AArch64 CurrentEL sysreg, Peter Maydell, 2014/02/15
- [Qemu-devel] [PATCH v3 04/31] target-arm: Implement AArch64 MIDR_EL1, Peter Maydell, 2014/02/15
- Re: [Qemu-devel] [PATCH v3 00/31] A64 system emulation prequisites, Peter Maydell, 2014/02/25