Re: [Qemu-devel] [PATCH v3 21/31] target-arm: Implement AArch64 DAIF system register

[Peter Maydell]

On 17 February 2014 00:17, Peter Crosthwaite
<address@hidden> wrote:
> On Sun, Feb 16, 2014 at 2:07 AM, Peter Maydell <address@hidden> wrote:
>> Implement the DAIF system register which is a view of the
>> DAIF bits in PSTATE.
>>
>> Signed-off-by: Peter Maydell <address@hidden>
>> Reviewed-by: Peter Crosthwaite <address@hidden>
>> ---
>>  target-arm/helper.c | 24 ++++++++++++++++++++++++
>>  1 file changed, 24 insertions(+)
>>
>> diff --git a/target-arm/helper.c b/target-arm/helper.c
>> index 367fbbe..c50ca5a 100644
>> --- a/target-arm/helper.c
>> +++ b/target-arm/helper.c
>> @@ -1589,6 +1589,25 @@ static void aa64_fpsr_write(CPUARMState *env, const 
>> ARMCPRegInfo *ri,
>>      vfp_set_fpsr(env, value);
>>  }
>>
>> +static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo 
>> *ri)
>> +{
>> +    if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UMA)) {
>> +        return CP_ACCESS_TRAP;
>> +    }
>> +    return CP_ACCESS_OK;
>> +}
>> +
>> +static uint64_t aa64_daif_read(CPUARMState *env, const ARMCPRegInfo *ri)
>> +{
>> +    return env->daif;
>> +}
>
> Is it better to just define the .fieldoffset and do away with the
> default-behaving read handler? My understanding is this will avoid a
> call out to helper context when running under TCG as well, leading to
> a slight perf increase.

Yeah; I think this was just a holdover from when it was reading
from pstate and so had to mask out the other bits.

thanks
-- PMM