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[Qemu-devel] [PULL 06/15] tcg/optimize: add known-zero bits compute for


From: Richard Henderson
Subject: [Qemu-devel] [PULL 06/15] tcg/optimize: add known-zero bits compute for load ops
Date: Mon, 17 Feb 2014 19:15:56 -0600

From: Aurelien Jarno <address@hidden>

Reviewed-by: Paolo Bonzini <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
 tcg/optimize.c | 26 +++++++++++++++++++++++++-
 1 file changed, 25 insertions(+), 1 deletion(-)

diff --git a/tcg/optimize.c b/tcg/optimize.c
index 1cf017a..1b9fea5 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -779,13 +779,37 @@ static TCGArg *tcg_constant_folding(TCGContext *s, 
uint16_t *tcg_opc_ptr,
             mask = temps[args[3]].mask | temps[args[4]].mask;
             break;
 
+        CASE_OP_32_64(ld8u):
+        case INDEX_op_qemu_ld8u:
+            mask = 0xff;
+            break;
+        CASE_OP_32_64(ld16u):
+        case INDEX_op_qemu_ld16u:
+            mask = 0xffff;
+            break;
+        case INDEX_op_ld32u_i64:
+#if TCG_TARGET_REG_BITS == 64
+        case INDEX_op_qemu_ld32u:
+#endif
+            mask = 0xffffffffu;
+            break;
+
+        CASE_OP_32_64(qemu_ld):
+            {
+                TCGMemOp mop = args[def->nb_oargs + def->nb_iargs];
+                if (!(mop & MO_SIGN)) {
+                    mask = (2ULL << ((8 << (mop & MO_SIZE)) - 1)) - 1;
+                }
+            }
+            break;
+
         default:
             break;
         }
 
         /* 32-bit ops (non 64-bit ops and non load/store ops) generate 32-bit
            results */
-        if (!(tcg_op_defs[op].flags & (TCG_OPF_CALL_CLOBBER | TCG_OPF_64BIT))) 
{
+        if (!(def->flags & (TCG_OPF_CALL_CLOBBER | TCG_OPF_64BIT))) {
             mask &= 0xffffffffu;
         }
 
-- 
1.8.5.3




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