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[Qemu-devel] [PATCH v4 18/21] target-arm: Move arm_log_exception() into
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH v4 18/21] target-arm: Move arm_log_exception() into internals.h |
Date: |
Thu, 6 Mar 2014 19:33:02 +0000 |
Move arm_log_exception() into internals.h so we can use it from
helper-a64.c for the AArch64 exception entry code.
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/helper.c | 31 -------------------------------
target-arm/internals.h | 31 +++++++++++++++++++++++++++++++
2 files changed, 31 insertions(+), 31 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 3a976f7..e461914 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2849,37 +2849,6 @@ static void do_v7m_exception_exit(CPUARMState *env)
pointer. */
}
-/* Exception names for debug logging; note that not all of these
- * precisely correspond to architectural exceptions.
- */
-static const char * const excnames[] = {
- [EXCP_UDEF] = "Undefined Instruction",
- [EXCP_SWI] = "SVC",
- [EXCP_PREFETCH_ABORT] = "Prefetch Abort",
- [EXCP_DATA_ABORT] = "Data Abort",
- [EXCP_IRQ] = "IRQ",
- [EXCP_FIQ] = "FIQ",
- [EXCP_BKPT] = "Breakpoint",
- [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",
- [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
- [EXCP_STREX] = "QEMU intercept of STREX",
-};
-
-static inline void arm_log_exception(int idx)
-{
- if (qemu_loglevel_mask(CPU_LOG_INT)) {
- const char *exc = NULL;
-
- if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
- exc = excnames[idx];
- }
- if (!exc) {
- exc = "unknown";
- }
- qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc);
- }
-}
-
void arm_v7m_cpu_do_interrupt(CPUState *cs)
{
ARMCPU *cpu = ARM_CPU(cs);
diff --git a/target-arm/internals.h b/target-arm/internals.h
index 97a76c2..e15136b 100644
--- a/target-arm/internals.h
+++ b/target-arm/internals.h
@@ -39,6 +39,37 @@ static inline bool excp_is_internal(int excp)
|| excp == EXCP_STREX;
}
+/* Exception names for debug logging; note that not all of these
+ * precisely correspond to architectural exceptions.
+ */
+static const char * const excnames[] = {
+ [EXCP_UDEF] = "Undefined Instruction",
+ [EXCP_SWI] = "SVC",
+ [EXCP_PREFETCH_ABORT] = "Prefetch Abort",
+ [EXCP_DATA_ABORT] = "Data Abort",
+ [EXCP_IRQ] = "IRQ",
+ [EXCP_FIQ] = "FIQ",
+ [EXCP_BKPT] = "Breakpoint",
+ [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",
+ [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
+ [EXCP_STREX] = "QEMU intercept of STREX",
+};
+
+static inline void arm_log_exception(int idx)
+{
+ if (qemu_loglevel_mask(CPU_LOG_INT)) {
+ const char *exc = NULL;
+
+ if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
+ exc = excnames[idx];
+ }
+ if (!exc) {
+ exc = "unknown";
+ }
+ qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc);
+ }
+}
+
/* Scale factor for generic timers, ie number of ns per tick.
* This gives a 62.5MHz timer.
*/
--
1.9.0
- Re: [Qemu-devel] [PATCH v4 12/21] target-arm: A64: Implement DC ZVA, (continued)
[Qemu-devel] [PATCH v4 09/21] target-arm: Fix VFP enables for AArch32 EL0 under AArch64 EL1, Peter Maydell, 2014/03/06
[Qemu-devel] [PATCH v4 17/21] target-arm: Implement AArch64 SPSR_EL1, Peter Maydell, 2014/03/06
[Qemu-devel] [PATCH v4 16/21] target-arm: Implement SP_EL0, SP_EL1, Peter Maydell, 2014/03/06
[Qemu-devel] [PATCH v4 19/21] target-arm: Implement AArch64 EL1 exception handling, Peter Maydell, 2014/03/06
[Qemu-devel] [PATCH v4 18/21] target-arm: Move arm_log_exception() into internals.h,
Peter Maydell <=
[Qemu-devel] [PATCH v4 21/21] hw/arm/virt: Add support for Cortex-A57, Peter Maydell, 2014/03/06
[Qemu-devel] [PATCH v4 04/21] target-arm: Provide correct syndrome information for cpreg access traps, Peter Maydell, 2014/03/06
[Qemu-devel] [PATCH v4 10/21] target-arm: Add v8 mmu translation support, Peter Maydell, 2014/03/06
[Qemu-devel] [PATCH v4 11/21] target-arm: Don't mention PMU in debug feature register, Peter Maydell, 2014/03/06