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[Qemu-devel] [PULL 099/130] target-ppc: Altivec 2.07: Change VMUL_DO to
From: |
Alexander Graf |
Subject: |
[Qemu-devel] [PULL 099/130] target-ppc: Altivec 2.07: Change VMUL_DO to Support 64-bit Integers |
Date: |
Fri, 7 Mar 2014 00:33:46 +0100 |
From: Tom Musta <address@hidden>
This VMUL_DO macro provides support for the various vmule* and vmulo*
instructions. These instructions multiply vector elements, producing
products that are one size larger; e.g. vmuleub multiplies unsigned 8-bit
elements and produces a 16 bit unsigned element.
The existing macro works correctly for the existing instructions (8-bit,
and 16-bit source elements) but does not work correctly for 32-bit
source elements.
This patch adds an explicit cast to the multiplicands, forcing them to be
of the target element type. This is required for the forthcoming patches
that add the vmul[eo][us]w instructions.
Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
---
target-ppc/int_helper.c | 26 ++++++++++++++------------
1 file changed, 14 insertions(+), 12 deletions(-)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index 3e36c0a..20d34e6 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -983,28 +983,30 @@ void helper_vmsumuhs(CPUPPCState *env, ppc_avr_t *r,
ppc_avr_t *a,
}
}
-#define VMUL_DO(name, mul_element, prod_element, evenp) \
+#define VMUL_DO(name, mul_element, prod_element, cast, evenp) \
void helper_v##name(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
{ \
int i; \
\
VECTOR_FOR_INORDER_I(i, prod_element) { \
if (evenp) { \
- r->prod_element[i] = a->mul_element[i * 2 + HI_IDX] * \
- b->mul_element[i * 2 + HI_IDX]; \
+ r->prod_element[i] = \
+ (cast)a->mul_element[i * 2 + HI_IDX] * \
+ (cast)b->mul_element[i * 2 + HI_IDX]; \
} else { \
- r->prod_element[i] = a->mul_element[i * 2 + LO_IDX] * \
- b->mul_element[i * 2 + LO_IDX]; \
+ r->prod_element[i] = \
+ (cast)a->mul_element[i * 2 + LO_IDX] * \
+ (cast)b->mul_element[i * 2 + LO_IDX]; \
} \
} \
}
-#define VMUL(suffix, mul_element, prod_element) \
- VMUL_DO(mule##suffix, mul_element, prod_element, 1) \
- VMUL_DO(mulo##suffix, mul_element, prod_element, 0)
-VMUL(sb, s8, s16)
-VMUL(sh, s16, s32)
-VMUL(ub, u8, u16)
-VMUL(uh, u16, u32)
+#define VMUL(suffix, mul_element, prod_element, cast) \
+ VMUL_DO(mule##suffix, mul_element, prod_element, cast, 1) \
+ VMUL_DO(mulo##suffix, mul_element, prod_element, cast, 0)
+VMUL(sb, s8, s16, int16_t)
+VMUL(sh, s16, s32, int32_t)
+VMUL(ub, u8, u16, uint16_t)
+VMUL(uh, u16, u32, uint32_t)
#undef VMUL_DO
#undef VMUL
--
1.8.1.4
- [Qemu-devel] [PULL 095/130] target-ppc: Altivec 2.07: Add Opcode Macro for VX Form Instructions, (continued)
- [Qemu-devel] [PULL 095/130] target-ppc: Altivec 2.07: Add Opcode Macro for VX Form Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 090/130] target-ppc: Add Store Quadword Conditional, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 097/130] target-ppc: Altivec 2.07: Vector Logical Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 098/130] target-ppc: Altivec 2.07: Add/Subtract Unsigned Doubleword Modulo, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 094/130] target-ppc: Altivec 2.07: Add Support for Dual Altivec Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 096/130] target-ppc: Altivec 2.07: Add Support for R-Form Dual Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 093/130] target-ppc: Altivec 2.07: Add GEN_VXFORM3, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 101/130] target-ppc: Altivec 2.07: vmuluw Instruction, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 104/130] target-ppc: Altivec 2.07: Vector Min/Max Doubleword Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 100/130] target-ppc: Altivec 2.07: Multiply Even/Odd Word Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 099/130] target-ppc: Altivec 2.07: Change VMUL_DO to Support 64-bit Integers,
Alexander Graf <=
- [Qemu-devel] [PULL 106/130] target-ppc: Altivec 2.07: Unpack Signed Word Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 102/130] target-ppc: Altivec 2.07: Add Vector Count Leading Zeroes, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 103/130] target-ppc: Altivec 2.07: Vector Population Count Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 107/130] target-ppc: Altivec 2.07: Vector Merge Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 109/130] target-ppc: Altivec 2.07: Vector Doubleword Rotate and Shift Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 105/130] target-ppc: Altivec 2.07: Pack Doubleword Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 108/130] target-ppc: Altivec 2.07: Change Bit Masks to Support 64-bit Rotates and Shifts, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 110/130] target-ppc: Altivec 2.07: Quadword Addition and Subtracation, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 111/130] target-ppc: Altivec 2.07: vbpermq Instruction, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 112/130] target-ppc: Altivec 2.07: Doubleword Compares, Alexander Graf, 2014/03/06