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[Qemu-devel] [PATCH 00/16] A64 Neon patches: sixth set
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 00/16] A64 Neon patches: sixth set |
Date: |
Sun, 9 Mar 2014 15:10:51 +0000 |
This is the sixth set of patches implementing more of the
Neon instructions for A64 (assuming I haven't lost count...)
PMULL is a fixed version of the patch from last time round which
doesn't pointlessly pass cpu_env to the helper; the rest are new.
Remaining unimplemented usermode instructions:
* crypto, CRC32 [these are optional extensions anyway]
* FCVTZS, FCVTZU, SQSHLU, SQSHL, UQSHL from the shift-imm
and scalar-shift-imm groups
* FRECPE, FRSQRTE, URECPE, URSQRTE (2-misc, scalar 2-misc)
* SUQADD, USQADD, SQABS, SQNEG (2-misc, scalar-2misc)
* SQXTN, SQXTUN, UQXTN (scalar-2misc; 2-misc versions already done)
Available for testing and review purposes at
git://git.linaro.org/people/peter.maydell/qemu-arm.git a64-neon-sixth-set
I'm aiming to get these into the 2.0 release so I'd
appreciate code review for these :-)
thanks
-- PMM
Alex Bennée (6):
target-arm: A64: Fix bug in add_sub_ext handling of rn
target-arm: A64: Add last AdvSIMD Integer to FP ops
target-arm: A64: Add FSQRT to C3.6.17 (two misc)
target-arm: A64: Add remaining CLS/Z vector ops
target-arm: A64: Saturating and narrowing shift ops
target-arm: A64: Add FRECPX (reciprocal exponent)
Peter Maydell (10):
target-arm: A64: Implement PMULL instruction
target-arm: A64: Implement SADDLP, UADDLP, SADALP, UADALP
target-arm: A64: Implement SHLL, SHLL2
target-arm: A64: Implement FCVT[NMAPZ][SU] SIMD instructions
target-arm: A64: Implement FCVTN
target-arm: A64: Implement FCVTL
target-arm: A64: List unsupported shift-imm opcodes
target-arm: A64: Implement SRI
target-arm: A64: Implement FRINT*
exec-all.h: Increase MAX_OP_PER_INSTR for ARM A64 decoder
include/exec/exec-all.h | 2 +-
target-arm/helper-a64.c | 155 ++++++++
target-arm/helper-a64.h | 9 +
target-arm/translate-a64.c | 942 ++++++++++++++++++++++++++++++++++++++++++---
target-arm/translate.c | 1 +
target-arm/translate.h | 6 +
6 files changed, 1066 insertions(+), 49 deletions(-)
--
1.9.0
- [Qemu-devel] [PATCH 00/16] A64 Neon patches: sixth set,
Peter Maydell <=
- [Qemu-devel] [PATCH 12/16] target-arm: A64: List unsupported shift-imm opcodes, Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 10/16] target-arm: A64: Implement FCVTN, Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 11/16] target-arm: A64: Implement FCVTL, Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 02/16] target-arm: A64: Fix bug in add_sub_ext handling of rn, Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 04/16] target-arm: A64: Add FSQRT to C3.6.17 (two misc), Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 07/16] target-arm: A64: Implement SADDLP, UADDLP, SADALP, UADALP, Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 08/16] target-arm: A64: Implement SHLL, SHLL2, Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 09/16] target-arm: A64: Implement FCVT[NMAPZ][SU] SIMD instructions, Peter Maydell, 2014/03/09