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Re: [Qemu-devel] [PATCH 09/16] target-arm: A64: Implement FCVT[NMAPZ][SU
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH 09/16] target-arm: A64: Implement FCVT[NMAPZ][SU] SIMD instructions |
Date: |
Tue, 11 Mar 2014 13:53:46 +0000 |
On 9 March 2014 15:11, Peter Maydell <address@hidden> wrote:
> Implement the floating-point-to-integer conversion instructions
> FCVT[NMAPZ][SU] in the 2-reg-misc and scalar-2-reg-misc
> categories.
>
> Signed-off-by: Peter Maydell <address@hidden>
> ---
> @@ -8573,6 +8657,11 @@ static void disas_simd_two_reg_misc(DisasContext *s,
> uint32_t insn)
> bool is_q = extract32(insn, 30, 1);
> int rn = extract32(insn, 5, 5);
> int rd = extract32(insn, 0, 5);
> + bool need_fpstatus = false;
> + bool need_rmode = false;
> + int rmode;
This needs to be "int rmode = -1;" since some versions
of gcc otherwise complain about maybe-used-uninitialized
(not actually true since on all code paths we set rmode
if setting need_rmode to true, and only use rmode if
need_rmode is set).
No idea why only this function and not the scalar_two_reg_misc
similar construct provokes the warning....
thanks
-- PMM
- [Qemu-devel] [PATCH 00/16] A64 Neon patches: sixth set, Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 12/16] target-arm: A64: List unsupported shift-imm opcodes, Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 10/16] target-arm: A64: Implement FCVTN, Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 11/16] target-arm: A64: Implement FCVTL, Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 02/16] target-arm: A64: Fix bug in add_sub_ext handling of rn, Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 04/16] target-arm: A64: Add FSQRT to C3.6.17 (two misc), Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 07/16] target-arm: A64: Implement SADDLP, UADDLP, SADALP, UADALP, Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 08/16] target-arm: A64: Implement SHLL, SHLL2, Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 09/16] target-arm: A64: Implement FCVT[NMAPZ][SU] SIMD instructions, Peter Maydell, 2014/03/09
- Re: [Qemu-devel] [PATCH 09/16] target-arm: A64: Implement FCVT[NMAPZ][SU] SIMD instructions,
Peter Maydell <=
- [Qemu-devel] [PATCH 13/16] target-arm: A64: Add FRECPX (reciprocal exponent), Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 05/16] target-arm: A64: Add remaining CLS/Z vector ops, Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 03/16] target-arm: A64: Add last AdvSIMD Integer to FP ops, Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 15/16] target-arm: A64: Implement FRINT*, Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 01/16] target-arm: A64: Implement PMULL instruction, Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 16/16] exec-all.h: Increase MAX_OP_PER_INSTR for ARM A64 decoder, Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 14/16] target-arm: A64: Implement SRI, Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 06/16] target-arm: A64: Saturating and narrowing shift ops, Peter Maydell, 2014/03/09