[Qemu-devel] [PATCH v2 6/7] target-arm: Added ADFSR/AIFSR and REVIDR

[Alvise Rigo]

These registers are required in TCG because they are migrated by KVM:
their absence from the cpreg table leads to a migration failure.

Signed-off-by: Alvise Rigo <address@hidden>
---
 target-arm/cpu.h    | 1 +
 target-arm/helper.c | 9 +++++++++
 2 files changed, 10 insertions(+)

diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index adcfa42..2381fc5 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -170,6 +170,7 @@ typedef struct CPUARMState {
     /* System control coprocessor (cp15) */
     struct {
         uint32_t c0_cpuid;
+        uint32_t c0_revid;
         uint64_t c0_cssel; /* Cache size selection.  */
         uint64_t c1_sys; /* System control register.  */
         uint64_t c1_coproc; /* Coprocessor access register.  */
diff --git a/target-arm/helper.c b/target-arm/helper.c
index daa707e..1fec33a 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1456,6 +1456,10 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
     { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
       .access = PL1_RW,
       .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
+    { .name = "ADFSR", .cp = 15, .crn = 5, .crm = 1, .opc1 = 0, .opc2 = 0,
+      .access = PL1_R, .resetvalue = 0, .type = ARM_CP_CONST, },
+    { .name = "AIFSR", .cp = 15, .crn = 5, .crm = 1, .opc1 = 0, .opc2 = 1,
+      .access = PL1_R, .resetvalue = 0, .type = ARM_CP_CONST, },
     { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
       .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el1),
@@ -2148,6 +2152,11 @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
               .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
               .type = ARM_CP_OVERRIDE },
+            { .name = "REVIDR",
+              .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 6,
+              .access = PL1_R, .resetvalue = 0,
+              .writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
+              .fieldoffset = offsetof(CPUARMState, cp15.c0_revid),},
             { .name = "MIDR_EL1", .state = ARM_CP_STATE_AA64,
               .opc0 = 3, .opc1 = 0, .opc2 = 0, .crn = 0, .crm = 0,
               .access = PL1_R, .resetvalue = cpu->midr, .type = ARM_CP_CONST },
-- 
1.8.3.2