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[Qemu-devel] [PATCH v5 37/37] target-arm: Dump 32-bit CPU state if 64 bi
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH v5 37/37] target-arm: Dump 32-bit CPU state if 64 bit CPU is in AArch32 |
Date: |
Fri, 28 Mar 2014 16:10:24 +0000 |
For system mode, we may have a 64 bit CPU which is currently executing
in AArch32 state; if we're dumping CPU state to the logs we should
therefore show the correct state for the current execution state,
rather than hardwiring it based on the type of the CPU. For consistency
with how we handle translation, we leave the 32 bit dump function
as the default, and have it hand off control to the 64 bit dump code
if we're in AArch64 mode.
Reported-by: Rob Herring <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/cpu-qom.h | 2 --
target-arm/cpu64.c | 1 -
target-arm/translate.c | 5 +++++
target-arm/translate.h | 8 ++++++++
4 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index 82f1bc7..edc7f26 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -200,8 +200,6 @@ void arm_gt_ptimer_cb(void *opaque);
void arm_gt_vtimer_cb(void *opaque);
#ifdef TARGET_AARCH64
-void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
- fprintf_function cpu_fprintf, int flags);
int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
index c673ac2..8daa622 100644
--- a/target-arm/cpu64.c
+++ b/target-arm/cpu64.c
@@ -188,7 +188,6 @@ static void aarch64_cpu_class_init(ObjectClass *oc, void
*data)
CPUClass *cc = CPU_CLASS(oc);
cc->do_interrupt = aarch64_cpu_do_interrupt;
- cc->dump_state = aarch64_cpu_dump_state;
cc->set_pc = aarch64_cpu_set_pc;
cc->gdb_read_register = aarch64_cpu_gdb_read_register;
cc->gdb_write_register = aarch64_cpu_gdb_write_register;
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 6ea2352..16a923c 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -11035,6 +11035,11 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f,
fprintf_function cpu_fprintf,
int i;
uint32_t psr;
+ if (is_a64(env)) {
+ aarch64_cpu_dump_state(cs, f, cpu_fprintf, flags);
+ return;
+ }
+
for(i=0;i<16;i++) {
cpu_fprintf(f, "R%02d=%08x", i, env->regs[i]);
if ((i % 4) == 3)
diff --git a/target-arm/translate.h b/target-arm/translate.h
index 3f7d5ca..34328f4 100644
--- a/target-arm/translate.h
+++ b/target-arm/translate.h
@@ -72,6 +72,8 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu,
TranslationBlock *tb,
bool search_pc);
void gen_a64_set_pc_im(uint64_t val);
+void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
+ fprintf_function cpu_fprintf, int flags);
#else
static inline void a64_translate_init(void)
{
@@ -86,6 +88,12 @@ static inline void gen_intermediate_code_internal_a64(ARMCPU
*cpu,
static inline void gen_a64_set_pc_im(uint64_t val)
{
}
+
+static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
+ fprintf_function cpu_fprintf,
+ int flags)
+{
+}
#endif
void arm_gen_test_cc(int cc, int label);
--
1.9.0
- [Qemu-devel] [PATCH v5 32/37] target-arm: Implement RVBAR register, (continued)
- [Qemu-devel] [PATCH v5 32/37] target-arm: Implement RVBAR register, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 25/37] target-arm: Implement AArch64 view of ACTLR, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 24/37] target-arm: Implement AArch64 view of CONTEXTIDR, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 01/37] target-arm: Split out private-to-target functions into internals.h, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 15/37] target-arm: Add AArch64 ELR_EL1 register., Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 35/37] target-arm: Make Cortex-A15 CBAR read-only, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 04/37] target-arm: Provide correct syndrome information for cpreg access traps, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 03/37] target-arm: Define exception record for AArch64 exceptions, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 28/37] target-arm: Don't expose wildcard ID register definitions for ARMv8, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 07/37] target-arm: A64: Correctly fault FP/Neon if CPACR.FPEN set, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 37/37] target-arm: Dump 32-bit CPU state if 64 bit CPU is in AArch32,
Peter Maydell <=
- [Qemu-devel] [PATCH v5 29/37] target-arm: Replace wildcarded cpreg definitions with precise ones for ARMv8, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 31/37] target-arm: Implement AArch64 address translation operations, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 33/37] target-arm: Implement Cortex-A57 implementation-defined system registers, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 14/37] target-arm: Implement AArch64 views of fault status and data registers, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 11/37] target-arm: Don't mention PMU in debug feature register, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 13/37] target-arm: Use dedicated CPU state fields for ARM946 access bit registers, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 05/37] target-arm: Add support for generating exceptions with syndrome information, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 12/37] target-arm: A64: Implement DC ZVA, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 17/37] target-arm: Implement AArch64 SPSR_EL1, Peter Maydell, 2014/03/28