[Qemu-devel] [PATCH 7/8] tcg-aarch64: Define TCG_TARGET_ITYPE_SIZE

[Richard Henderson]

Signed-off-by: Richard Henderson <address@hidden>
---
 tcg/aarch64/tcg-target.c | 38 ++++++++++++++++----------------------
 tcg/aarch64/tcg-target.h |  1 +
 2 files changed, 17 insertions(+), 22 deletions(-)

diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index 661a5af..2614201 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -71,27 +71,23 @@ static const int tcg_target_call_oarg_regs[1] = {
 # endif
 #endif
 
-static inline void reloc_pc26(void *code_ptr, intptr_t target)
+static inline void reloc_pc26(tcg_itype *code_ptr, intptr_t target)
 {
     intptr_t offset = (target - (intptr_t)code_ptr) / 4;
     /* read instruction, mask away previous PC_REL26 parameter contents,
        set the proper offset, then write back the instruction. */
-    uint32_t insn = *(uint32_t *)code_ptr;
-    insn = deposit32(insn, 0, 26, offset);
-    *(uint32_t *)code_ptr = insn;
+    *code_ptr = deposit32(*code_ptr, 0, 26, offset);
 }
 
-static inline void reloc_pc19(void *code_ptr, intptr_t target)
+static inline void reloc_pc19(tcg_itype *code_ptr, intptr_t target)
 {
     intptr_t offset = (target - (intptr_t)code_ptr) / 4;
     /* read instruction, mask away previous PC_REL19 parameter contents,
        set the proper offset, then write back the instruction. */
-    uint32_t insn = *(uint32_t *)code_ptr;
-    insn = deposit32(insn, 5, 19, offset);
-    *(uint32_t *)code_ptr = insn;
+    *code_ptr = deposit32(*code_ptr, 5, 19, offset);
 }
 
-static inline void patch_reloc(uint8_t *code_ptr, int type,
+static inline void patch_reloc(tcg_itype *code_ptr, int type,
                                intptr_t value, intptr_t addend)
 {
     value += addend;
@@ -104,7 +100,6 @@ static inline void patch_reloc(uint8_t *code_ptr, int type,
     case R_AARCH64_CONDBR19:
         reloc_pc19(code_ptr, value);
         break;
-
     default:
         tcg_abort();
     }
@@ -409,8 +404,7 @@ aarch64_ldst_get_type(TCGOpcode tcg_op)
 
 static inline uint32_t tcg_in32(TCGContext *s)
 {
-    uint32_t v = *(uint32_t *)s->code_ptr;
-    return v;
+    return *s->code_ptr;
 }
 
 /* Emit an opcode with "type-checking" of the format.  */
@@ -783,7 +777,7 @@ void aarch64_tb_set_jmp_target(uintptr_t jmp_addr, 
uintptr_t addr)
         tcg_abort();
     }
 
-    patch_reloc((uint8_t *)jmp_addr, R_AARCH64_JUMP26, target, 0);
+    reloc_pc26((tcg_itype *)jmp_addr, target);
     flush_icache_range(jmp_addr, jmp_addr + 4);
 }
 
@@ -985,7 +979,7 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, 
TCGLabelQemuLdst *lb)
 static void add_qemu_ldst_label(TCGContext *s, int is_ld, int opc,
                                 TCGReg data_reg, TCGReg addr_reg,
                                 int mem_index,
-                                uint8_t *raddr, uint8_t *label_ptr)
+                                tcg_itype *raddr, tcg_itype *label_ptr)
 {
     TCGLabelQemuLdst *label = new_ldst_label(s);
 
@@ -1003,7 +997,7 @@ static void add_qemu_ldst_label(TCGContext *s, int is_ld, 
int opc,
    the slow path. Generated code returns the host addend in X1,
    clobbers X0,X2,X3,TMP. */
 static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg,
-            int s_bits, uint8_t **label_ptr, int mem_index, int is_read)
+            int s_bits, tcg_itype **label_ptr, int mem_index, int is_read)
 {
     TCGReg base = TCG_AREG0;
     int tlb_offset = is_read ?
@@ -1140,7 +1134,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg 
*args, int opc)
     TCGReg addr_reg, data_reg;
 #ifdef CONFIG_SOFTMMU
     int mem_index, s_bits;
-    uint8_t *label_ptr;
+    tcg_itype *label_ptr;
 #endif
     data_reg = args[0];
     addr_reg = args[1];
@@ -1163,7 +1157,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg 
*args, int opc)
     TCGReg addr_reg, data_reg;
 #ifdef CONFIG_SOFTMMU
     int mem_index, s_bits;
-    uint8_t *label_ptr;
+    tcg_itype *label_ptr;
 #endif
     data_reg = args[0];
     addr_reg = args[1];
@@ -1182,7 +1176,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg 
*args, int opc)
 #endif /* CONFIG_SOFTMMU */
 }
 
-static uint8_t *tb_ret_addr;
+static intptr_t tb_ret_addr;
 
 /* callee stack use example:
    stp     x29, x30, [sp,#-32]!
@@ -1255,7 +1249,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
     switch (opc) {
     case INDEX_op_exit_tb:
         tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_X0, a0);
-        tcg_out_goto(s, (intptr_t)tb_ret_addr);
+        tcg_out_goto(s, tb_ret_addr);
         break;
 
     case INDEX_op_goto_tb:
@@ -1263,11 +1257,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
 #error "USE_DIRECT_JUMP required for aarch64"
 #endif
         assert(s->tb_jmp_offset != NULL); /* consistency for USE_DIRECT_JUMP */
-        s->tb_jmp_offset[a0] = s->code_ptr - s->code_buf;
+        s->tb_jmp_offset[a0] = (intptr_t)s->code_ptr - (intptr_t)s->code_buf;
         /* actual branch destination will be patched by
            aarch64_tb_set_jmp_target later, beware retranslation. */
         tcg_out_goto_noaddr(s);
-        s->tb_next_offset[a0] = s->code_ptr - s->code_buf;
+        s->tb_next_offset[a0] = (intptr_t)s->code_ptr - (intptr_t)s->code_buf;
         break;
 
     case INDEX_op_call:
@@ -1820,7 +1814,7 @@ static void tcg_target_qemu_prologue(TCGContext *s)
     tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
     tcg_out_gotor(s, tcg_target_call_iarg_regs[1]);
 
-    tb_ret_addr = s->code_ptr;
+    tb_ret_addr = (intptr_t)s->code_ptr;
 
     /* Remove TCG locals stack space.  */
     tcg_out_insn(s, 3401, ADDI, TCG_TYPE_I64, TCG_REG_SP, TCG_REG_SP,
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index 988983e..b6cc72d 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -15,6 +15,7 @@
 
 #undef TCG_TARGET_WORDS_BIGENDIAN
 #undef TCG_TARGET_STACK_GROWSUP
+#define TCG_TARGET_ITYPE_SIZE 4
 
 typedef enum {
     TCG_REG_X0, TCG_REG_X1, TCG_REG_X2, TCG_REG_X3, TCG_REG_X4,
-- 
1.9.0