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Re: [Qemu-devel] [PATCH v5 08/37] target-arm: A64: Add assertion that FP
From: |
Peter Crosthwaite |
Subject: |
Re: [Qemu-devel] [PATCH v5 08/37] target-arm: A64: Add assertion that FP access was checked |
Date: |
Tue, 1 Apr 2014 13:24:33 +1000 |
On Sat, Mar 29, 2014 at 2:09 AM, Peter Maydell <address@hidden> wrote:
> Because unallocated encodings generate different exception syndrome
> information from traps due to FP being disabled, we can't do a single
> "is fp access disabled" check at a high level in the decode tree.
> To help in catching bugs where the access check was forgotten in some
> code path, we set this flag when the access check is done, and assert
> that it is set at the point where we actually touch the FP regs.
>
> This requires us to pass the DisasContext to the vec_reg_offset
> and fp_reg_offset functions.
>
> Signed-off-by: Peter Maydell <address@hidden>
> ---
> target-arm/translate-a64.c | 74
> +++++++++++++++++++++++++++++++---------------
> target-arm/translate.h | 8 +++++
> 2 files changed, 58 insertions(+), 24 deletions(-)
>
> diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
> index 2f67af3..b7cf907 100644
> --- a/target-arm/translate-a64.c
> +++ b/target-arm/translate-a64.c
> @@ -353,11 +353,29 @@ static TCGv_i64 read_cpu_reg_sp(DisasContext *s, int
> reg, int sf)
> return v;
> }
>
> +/* We should have at some point before trying to access an FP register
> + * done the necessary access check, so assert that (a) we did the check
> + * and (b) we didn't then just plough ahead anyway if it failed.
Might as well do the listing of "(a) foo" and "(b) bar" on new lines
for readability.
> + *.Print the instruction pattern in the abort message so we can figure
Extraneous "."
Otherwise,
Reviewed-by: Peter Crosthwaite <address@hidden>
> + * out what we need to fix if a user encounters this problem in the wild.
> + */
- [Qemu-devel] [PATCH v5 12/37] target-arm: A64: Implement DC ZVA, (continued)
- [Qemu-devel] [PATCH v5 12/37] target-arm: A64: Implement DC ZVA, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 17/37] target-arm: Implement AArch64 SPSR_EL1, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 23/37] target-arm: Implement AArch64 views of AArch32 ID registers, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 21/37] target-arm: Add Cortex-A57 processor, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 02/37] target-arm: Implement AArch64 DAIF system register, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 20/37] target-arm: Implement ARMv8 MVFR registers, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 09/37] target-arm: Fix VFP enables for AArch32 EL0 under AArch64 EL1, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 08/37] target-arm: A64: Add assertion that FP access was checked, Peter Maydell, 2014/03/28
- Re: [Qemu-devel] [PATCH v5 08/37] target-arm: A64: Add assertion that FP access was checked,
Peter Crosthwaite <=
- [Qemu-devel] [PATCH v5 06/37] target-arm: Provide syndrome information for MMU faults, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 19/37] target-arm: Implement AArch64 EL1 exception handling, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 36/37] target-arm: Handle the CPU being in AArch32 mode in the AArch64 set_pc, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 27/37] target-arm: Remove THUMB2EE feature from AArch64 'any' CPU, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 30/37] target-arm: Implement auxiliary fault status registers, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 18/37] target-arm: Move arm_log_exception() into internals.h, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 26/37] target-arm: Implement ISR_EL1 register, Peter Maydell, 2014/03/28