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[Qemu-devel] [PATCH v6 18/37] target-arm: Move arm_log_exception() into
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH v6 18/37] target-arm: Move arm_log_exception() into internals.h |
Date: |
Thu, 10 Apr 2014 17:15:17 +0100 |
Move arm_log_exception() into internals.h so we can use it from
helper-a64.c for the AArch64 exception entry code.
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/helper.c | 31 -------------------------------
target-arm/internals.h | 31 +++++++++++++++++++++++++++++++
2 files changed, 31 insertions(+), 31 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 68f8c6a..e9b64f3 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2957,37 +2957,6 @@ static void do_v7m_exception_exit(CPUARMState *env)
pointer. */
}
-/* Exception names for debug logging; note that not all of these
- * precisely correspond to architectural exceptions.
- */
-static const char * const excnames[] = {
- [EXCP_UDEF] = "Undefined Instruction",
- [EXCP_SWI] = "SVC",
- [EXCP_PREFETCH_ABORT] = "Prefetch Abort",
- [EXCP_DATA_ABORT] = "Data Abort",
- [EXCP_IRQ] = "IRQ",
- [EXCP_FIQ] = "FIQ",
- [EXCP_BKPT] = "Breakpoint",
- [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",
- [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
- [EXCP_STREX] = "QEMU intercept of STREX",
-};
-
-static inline void arm_log_exception(int idx)
-{
- if (qemu_loglevel_mask(CPU_LOG_INT)) {
- const char *exc = NULL;
-
- if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
- exc = excnames[idx];
- }
- if (!exc) {
- exc = "unknown";
- }
- qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc);
- }
-}
-
void arm_v7m_cpu_do_interrupt(CPUState *cs)
{
ARMCPU *cpu = ARM_CPU(cs);
diff --git a/target-arm/internals.h b/target-arm/internals.h
index de79dfc..d63a975 100644
--- a/target-arm/internals.h
+++ b/target-arm/internals.h
@@ -39,6 +39,37 @@ static inline bool excp_is_internal(int excp)
|| excp == EXCP_STREX;
}
+/* Exception names for debug logging; note that not all of these
+ * precisely correspond to architectural exceptions.
+ */
+static const char * const excnames[] = {
+ [EXCP_UDEF] = "Undefined Instruction",
+ [EXCP_SWI] = "SVC",
+ [EXCP_PREFETCH_ABORT] = "Prefetch Abort",
+ [EXCP_DATA_ABORT] = "Data Abort",
+ [EXCP_IRQ] = "IRQ",
+ [EXCP_FIQ] = "FIQ",
+ [EXCP_BKPT] = "Breakpoint",
+ [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",
+ [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
+ [EXCP_STREX] = "QEMU intercept of STREX",
+};
+
+static inline void arm_log_exception(int idx)
+{
+ if (qemu_loglevel_mask(CPU_LOG_INT)) {
+ const char *exc = NULL;
+
+ if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
+ exc = excnames[idx];
+ }
+ if (!exc) {
+ exc = "unknown";
+ }
+ qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc);
+ }
+}
+
/* Scale factor for generic timers, ie number of ns per tick.
* This gives a 62.5MHz timer.
*/
--
1.9.1
- [Qemu-devel] [PATCH v6 26/37] target-arm: Implement ISR_EL1 register, (continued)
- [Qemu-devel] [PATCH v6 26/37] target-arm: Implement ISR_EL1 register, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 09/37] target-arm: Fix VFP enables for AArch32 EL0 under AArch64 EL1, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 01/37] target-arm: Split out private-to-target functions into internals.h, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 11/37] target-arm: Don't mention PMU in debug feature register, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 37/37] target-arm: Dump 32-bit CPU state if 64 bit CPU is in AArch32, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 13/37] target-arm: Use dedicated CPU state fields for ARM946 access bit registers, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 29/37] target-arm: Replace wildcarded cpreg definitions with precise ones for ARMv8, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 10/37] target-arm: Add v8 mmu translation support, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 18/37] target-arm: Move arm_log_exception() into internals.h,
Peter Maydell <=
- [Qemu-devel] [PATCH v6 24/37] target-arm: Implement AArch64 view of CONTEXTIDR, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 04/37] target-arm: Provide correct syndrome information for cpreg access traps, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 03/37] target-arm: Define exception record for AArch64 exceptions, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 05/37] target-arm: Add support for generating exceptions with syndrome information, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 06/37] target-arm: Provide syndrome information for MMU faults, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 17/37] target-arm: Implement AArch64 SPSR_EL1, Peter Maydell, 2014/04/10