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Re: [Qemu-devel] [PATCH v6 25/37] target-arm: Implement AArch64 view of


From: Peter Crosthwaite
Subject: Re: [Qemu-devel] [PATCH v6 25/37] target-arm: Implement AArch64 view of ACTLR
Date: Mon, 14 Apr 2014 16:19:45 +1000

On Fri, Apr 11, 2014 at 2:15 AM, Peter Maydell <address@hidden> wrote:
> Implement the AArch64 view of the ACTLR (auxiliary control
> register). Note that QEMU internally tends to call this
> AUXCR for historical reasons.
>

So Ive noticed that in recent patches that where registers have
multiple names, new trumps old. Any particular reason to not update as
done in a fair few other patches?

> Signed-off-by: Peter Maydell <address@hidden>
> ---
>  target-arm/helper.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 10300aa..f2e6f17 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -2316,7 +2316,8 @@ void register_cp_regs_for_features(ARMCPU *cpu)
>
>      if (arm_feature(env, ARM_FEATURE_AUXCR)) {
>          ARMCPRegInfo auxcr = {
> -            .name = "AUXCR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 
> = 1,
> +            .name = "AUXCR", .state = ARM_CP_STATE_BOTH,

With change of name to "ACTLR" or "ACTLR_EL1":

Reviewed-by: Peter Crosthwaite <address@hidden>

> +            .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1,
>              .access = PL1_RW, .type = ARM_CP_CONST,
>              .resetvalue = cpu->reset_auxcr
>          };
> --
> 1.9.1
>
>



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