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Re: [Qemu-devel] [PATCH v3 01/26] tcg-aarch64: Properly detect SIGSEGV w


From: Claudio Fontana
Subject: Re: [Qemu-devel] [PATCH v3 01/26] tcg-aarch64: Properly detect SIGSEGV writes
Date: Mon, 14 Apr 2014 13:32:09 +0200
User-agent: Mozilla/5.0 (Windows NT 6.1; rv:24.0) Gecko/20100101 Thunderbird/24.0.1

On 07.04.2014 18:33, Richard Henderson wrote:
> On 04/07/2014 12:58 AM, Claudio Fontana wrote:
>>> +                || (insn & 0x3bc00000) == 0x28400000   /* C3.3.7 */
>>
>> I think the Load (L) bit should be 0 here so
>>
>> == 0x28000000
> 
> Oops.  Fixed.
> 
>>
>>> +                || (insn & 0x3be00c00) == 0x38000400   /* C3.3.8 */
>>
>> With V=1, an opc of 0b10 is also a write, I think. It's the 128bit FP/SIMD 
>> STR.
> 
> Exactly, that's why I'm masking it out, to ignore it.
> 
>  insn  =  size 1 1   1 v 0 0 ...
>  mask  =   0 0 1 1   1 0 1 1 ...  = 0x3b...
>  equal =   0 0 1 1   1 0 0 0 ...  = 0x38...
> 
> 
> r~
> 

the problem is not in the two nibbles you show, but in the third nibble:
31 30 29 28  27 26 25 24  23 22 21 20
 size  1  1   1  v  0  0   opc   0  x

the third nibble in your mask is 'E' and the expected result is 0, which forces 
opc to be 0 for writes.
However, for 128bit SIMD STR, the opc is 2 (0b10).

Ciao,

Claudio





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