[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 36/51] target-arm: Dump 32-bit CPU state if 64 bit CP
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 36/51] target-arm: Dump 32-bit CPU state if 64 bit CPU is in AArch32 |
Date: |
Thu, 17 Apr 2014 11:33:51 +0100 |
For system mode, we may have a 64 bit CPU which is currently executing
in AArch32 state; if we're dumping CPU state to the logs we should
therefore show the correct state for the current execution state,
rather than hardwiring it based on the type of the CPU. For consistency
with how we handle translation, we leave the 32 bit dump function
as the default, and have it hand off control to the 64 bit dump code
if we're in AArch64 mode.
Reported-by: Rob Herring <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/cpu-qom.h | 2 --
target-arm/cpu64.c | 1 -
target-arm/translate.c | 5 +++++
target-arm/translate.h | 8 ++++++++
4 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index 82f1bc7..edc7f26 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -200,8 +200,6 @@ void arm_gt_ptimer_cb(void *opaque);
void arm_gt_vtimer_cb(void *opaque);
#ifdef TARGET_AARCH64
-void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
- fprintf_function cpu_fprintf, int flags);
int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
index c673ac2..8daa622 100644
--- a/target-arm/cpu64.c
+++ b/target-arm/cpu64.c
@@ -188,7 +188,6 @@ static void aarch64_cpu_class_init(ObjectClass *oc, void
*data)
CPUClass *cc = CPU_CLASS(oc);
cc->do_interrupt = aarch64_cpu_do_interrupt;
- cc->dump_state = aarch64_cpu_dump_state;
cc->set_pc = aarch64_cpu_set_pc;
cc->gdb_read_register = aarch64_cpu_gdb_read_register;
cc->gdb_write_register = aarch64_cpu_gdb_write_register;
diff --git a/target-arm/translate.c b/target-arm/translate.c
index f7b5daf..0c08cc1 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -11047,6 +11047,11 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f,
fprintf_function cpu_fprintf,
int i;
uint32_t psr;
+ if (is_a64(env)) {
+ aarch64_cpu_dump_state(cs, f, cpu_fprintf, flags);
+ return;
+ }
+
for(i=0;i<16;i++) {
cpu_fprintf(f, "R%02d=%08x", i, env->regs[i]);
if ((i % 4) == 3)
diff --git a/target-arm/translate.h b/target-arm/translate.h
index 3f7d5ca..34328f4 100644
--- a/target-arm/translate.h
+++ b/target-arm/translate.h
@@ -72,6 +72,8 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu,
TranslationBlock *tb,
bool search_pc);
void gen_a64_set_pc_im(uint64_t val);
+void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
+ fprintf_function cpu_fprintf, int flags);
#else
static inline void a64_translate_init(void)
{
@@ -86,6 +88,12 @@ static inline void gen_intermediate_code_internal_a64(ARMCPU
*cpu,
static inline void gen_a64_set_pc_im(uint64_t val)
{
}
+
+static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
+ fprintf_function cpu_fprintf,
+ int flags)
+{
+}
#endif
void arm_gen_test_cc(int cc, int label);
--
1.9.1
- [Qemu-devel] [PULL 45/51] allwinner-emac: update irq status after writes to interrupt registers, (continued)
- [Qemu-devel] [PULL 45/51] allwinner-emac: update irq status after writes to interrupt registers, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 44/51] allwinner-emac: set autonegotiation complete bit on link up, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 43/51] allwinner-a10-pit: implement prescaler and source selection, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 41/51] allwinner-a10-pit: avoid generation of spurious interrupts, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 42/51] allwinner-a10-pit: use level triggered interrupts, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 01/51] target-arm: Split out private-to-target functions into internals.h, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 39/51] allwinner-a10-pic: set vector address when an interrupt is pending, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 46/51] misc: zynq-slcr: Rewrite, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 38/51] timer: cadence_ttc: Fix match register write logic, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 37/51] target-arm/gdbstub64.c: remove useless 'break' statement., Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 36/51] target-arm: Dump 32-bit CPU state if 64 bit CPU is in AArch32,
Peter Maydell <=
- [Qemu-devel] [PULL 34/51] target-arm: Make Cortex-A15 CBAR read-only, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 33/51] target-arm: Implement CBAR for Cortex-A57, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 35/51] target-arm: Handle the CPU being in AArch32 mode in the AArch64 set_pc, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 32/51] target-arm: Implement Cortex-A57 implementation-defined system registers, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 31/51] target-arm: Implement RVBAR register, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 29/51] target-arm: Implement auxiliary fault status registers, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 30/51] target-arm: Implement AArch64 address translation operations, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 40/51] allwinner-a10-pic: fix behaviour of pending register, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 27/51] target-arm: Don't expose wildcard ID register definitions for ARMv8, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 28/51] target-arm: Replace wildcarded cpreg definitions with precise ones for ARMv8, Peter Maydell, 2014/04/17