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[Qemu-devel] [PULL 21/51] target-arm: Add Cortex-A57 processor
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 21/51] target-arm: Add Cortex-A57 processor |
Date: |
Thu, 17 Apr 2014 11:33:36 +0100 |
Add Cortex-A57 processor.
Signed-off-by: Peter Maydell <address@hidden>
Acked-by: Peter Crosthwaite <address@hidden>
---
target-arm/cpu64.c | 43 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
index d4fb1de..5be7d72 100644
--- a/target-arm/cpu64.c
+++ b/target-arm/cpu64.c
@@ -32,6 +32,48 @@ static inline void set_feature(CPUARMState *env, int feature)
env->features |= 1ULL << feature;
}
+static void aarch64_a57_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ set_feature(&cpu->env, ARM_FEATURE_V8);
+ set_feature(&cpu->env, ARM_FEATURE_VFP4);
+ set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+ cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
+ cpu->midr = 0x411fd070;
+ cpu->reset_fpsid = 0x41034070;
+ cpu->mvfr0 = 0x10110222;
+ cpu->mvfr1 = 0x12111111;
+ cpu->mvfr2 = 0x00000043;
+ cpu->ctr = 0x8444c004;
+ cpu->reset_sctlr = 0x00c50838;
+ cpu->id_pfr0 = 0x00000131;
+ cpu->id_pfr1 = 0x00011011;
+ cpu->id_dfr0 = 0x03010066;
+ cpu->id_afr0 = 0x00000000;
+ cpu->id_mmfr0 = 0x10101105;
+ cpu->id_mmfr1 = 0x40000000;
+ cpu->id_mmfr2 = 0x01260000;
+ cpu->id_mmfr3 = 0x02102211;
+ cpu->id_isar0 = 0x02101110;
+ cpu->id_isar1 = 0x13112111;
+ cpu->id_isar2 = 0x21232042;
+ cpu->id_isar3 = 0x01112131;
+ cpu->id_isar4 = 0x00011142;
+ cpu->id_aa64pfr0 = 0x00002222;
+ cpu->id_aa64dfr0 = 0x10305106;
+ cpu->id_aa64isar0 = 0x00010000;
+ cpu->id_aa64mmfr0 = 0x00001124;
+ cpu->clidr = 0x0a200023;
+ cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
+ cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
+ cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
+ cpu->dcz_blocksize = 4; /* 64 bytes */
+}
+
#ifdef CONFIG_USER_ONLY
static void aarch64_any_initfn(Object *obj)
{
@@ -57,6 +99,7 @@ typedef struct ARMCPUInfo {
} ARMCPUInfo;
static const ARMCPUInfo aarch64_cpus[] = {
+ { .name = "cortex-a57", .initfn = aarch64_a57_initfn },
#ifdef CONFIG_USER_ONLY
{ .name = "any", .initfn = aarch64_any_initfn },
#endif
--
1.9.1
- [Qemu-devel] [PULL 29/51] target-arm: Implement auxiliary fault status registers, (continued)
- [Qemu-devel] [PULL 29/51] target-arm: Implement auxiliary fault status registers, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 30/51] target-arm: Implement AArch64 address translation operations, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 40/51] allwinner-a10-pic: fix behaviour of pending register, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 27/51] target-arm: Don't expose wildcard ID register definitions for ARMv8, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 28/51] target-arm: Replace wildcarded cpreg definitions with precise ones for ARMv8, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 26/51] target-arm: Remove THUMB2EE feature from AArch64 'any' CPU, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 24/51] target-arm: Implement AArch64 view of ACTLR, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 20/51] target-arm: Implement ARMv8 MVFR registers, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 25/51] target-arm: Implement ISR_EL1 register, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 18/51] target-arm: Move arm_log_exception() into internals.h, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 21/51] target-arm: Add Cortex-A57 processor,
Peter Maydell <=
- [Qemu-devel] [PULL 19/51] target-arm: Implement AArch64 EL1 exception handling, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 22/51] target-arm: Implement AArch64 views of AArch32 ID registers, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 17/51] target-arm: Implement AArch64 SPSR_EL1, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 15/51] target-arm: Add AArch64 ELR_EL1 register., Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 16/51] target-arm: Implement SP_EL0, SP_EL1, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 23/51] target-arm: Implement AArch64 view of CONTEXTIDR, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 13/51] target-arm: Use dedicated CPU state fields for ARM946 access bit registers, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 14/51] target-arm: Implement AArch64 views of fault status and data registers, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 09/51] target-arm: Fix VFP enables for AArch32 EL0 under AArch64 EL1, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 11/51] target-arm: Don't mention PMU in debug feature register, Peter Maydell, 2014/04/17