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[Qemu-devel] [PATCH 40/40] target-alpha: Remove cpu_unique, cpu_sysval,
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 40/40] target-alpha: Remove cpu_unique, cpu_sysval, cpu_usp |
Date: |
Thu, 17 Apr 2014 12:33:15 -0700 |
Technically, these variables could have been referenced both via
offsets from env and as TCG registers, which would be illegal.
Of course, that could only be done from PALcode, and ours doesn't
do that.
But honestly, these are used infrequently enough that they don't
really need to be TCG registers. We wind up with exactly the same
code if we follow the letter of the law and issue explicit ld/st.
Signed-off-by: Richard Henderson <address@hidden>
---
target-alpha/translate.c | 37 ++++++++++++++++++-------------------
1 file changed, 18 insertions(+), 19 deletions(-)
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 80a40d2..d0357ff 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -89,11 +89,6 @@ static TCGv cpu_pc;
static TCGv cpu_lock_addr;
static TCGv cpu_lock_st_addr;
static TCGv cpu_lock_value;
-static TCGv cpu_unique;
-#ifndef CONFIG_USER_ONLY
-static TCGv cpu_sysval;
-static TCGv cpu_usp;
-#endif
#include "exec/gen-icount.h"
@@ -107,11 +102,6 @@ void alpha_translate_init(void)
DEF_VAR(lock_addr),
DEF_VAR(lock_st_addr),
DEF_VAR(lock_value),
- DEF_VAR(unique),
-#ifndef CONFIG_USER_ONLY
- DEF_VAR(sysval),
- DEF_VAR(usp),
-#endif
};
#undef DEF_VAR
@@ -1139,11 +1129,13 @@ static ExitStatus gen_call_pal(DisasContext *ctx, int
palcode)
break;
case 0x9E:
/* RDUNIQUE */
- tcg_gen_mov_i64(cpu_ir[IR_V0], cpu_unique);
+ tcg_gen_ld_i64(cpu_ir[IR_V0], cpu_env,
+ offsetof(CPUAlphaState, unique));
break;
case 0x9F:
/* WRUNIQUE */
- tcg_gen_mov_i64(cpu_unique, cpu_ir[IR_A0]);
+ tcg_gen_st_i64(cpu_ir[IR_A0], cpu_env,
+ offsetof(CPUAlphaState, unique));
break;
default:
palcode &= 0xbf;
@@ -1166,15 +1158,18 @@ static ExitStatus gen_call_pal(DisasContext *ctx, int
palcode)
break;
case 0x2D:
/* WRVPTPTR */
- tcg_gen_st_i64(cpu_ir[IR_A0], cpu_env, offsetof(CPUAlphaState,
vptptr));
+ tcg_gen_st_i64(cpu_ir[IR_A0], cpu_env,
+ offsetof(CPUAlphaState, vptptr));
break;
case 0x31:
/* WRVAL */
- tcg_gen_mov_i64(cpu_sysval, cpu_ir[IR_A0]);
+ tcg_gen_st_i64(cpu_ir[IR_A0], cpu_env,
+ offsetof(CPUAlphaState, sysval));
break;
case 0x32:
/* RDVAL */
- tcg_gen_mov_i64(cpu_ir[IR_V0], cpu_sysval);
+ tcg_gen_ld_i64(cpu_ir[IR_V0], cpu_env,
+ offsetof(CPUAlphaState, sysval));
break;
case 0x35: {
@@ -1183,7 +1178,8 @@ static ExitStatus gen_call_pal(DisasContext *ctx, int
palcode)
/* Note that we already know we're in kernel mode, so we know
that PS only contains the 3 IPL bits. */
- tcg_gen_ld8u_i64(cpu_ir[IR_V0], cpu_env, offsetof(CPUAlphaState,
ps));
+ tcg_gen_ld8u_i64(cpu_ir[IR_V0], cpu_env,
+ offsetof(CPUAlphaState, ps));
/* But make sure and store only the 3 IPL bits from the user. */
tmp = tcg_temp_new();
@@ -1195,15 +1191,18 @@ static ExitStatus gen_call_pal(DisasContext *ctx, int
palcode)
case 0x36:
/* RDPS */
- tcg_gen_ld8u_i64(cpu_ir[IR_V0], cpu_env, offsetof(CPUAlphaState,
ps));
+ tcg_gen_ld8u_i64(cpu_ir[IR_V0], cpu_env,
+ offsetof(CPUAlphaState, ps));
break;
case 0x38:
/* WRUSP */
- tcg_gen_mov_i64(cpu_usp, cpu_ir[IR_A0]);
+ tcg_gen_st_i64(cpu_ir[IR_A0], cpu_env,
+ offsetof(CPUAlphaState, usp));
break;
case 0x3A:
/* RDUSP */
- tcg_gen_mov_i64(cpu_ir[IR_V0], cpu_usp);
+ tcg_gen_st_i64(cpu_ir[IR_V0], cpu_env,
+ offsetof(CPUAlphaState, usp));
break;
case 0x3C:
/* WHAMI */
--
1.9.0
- [Qemu-devel] [PATCH 27/40] target-alpha: Convert ARITH3 to source/sink, (continued)
- [Qemu-devel] [PATCH 27/40] target-alpha: Convert ARITH3 to source/sink, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 29/40] target-alpha: Convert gen_ieee_input to source/sink, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 28/40] target-alpha: Convert MVIOP2 to source/sink, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 31/40] target-alpha: Convert gen_bcond to source/sink, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 30/40] target-alpha: Convert most ieee insns to source/sink, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 32/40] target-alpha: Convert gen_fcmov to source/sink, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 33/40] target-alpha: Convert gen_fcvtlq/ql to source/sink, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 34/40] target-alpha: Convert gen_cpys et al to source/sink, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 38/40] target-alpha: Don't issue goto_tb under singlestep, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 39/40] target-alpha: Tidy alpha_translate_init, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 40/40] target-alpha: Remove cpu_unique, cpu_sysval, cpu_usp,
Richard Henderson <=
- [Qemu-devel] [PATCH 35/40] target-alpha: Convert mfpr/mtpr to source/sink, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 37/40] target-alpha: Use non-local temps for zero/sink, Richard Henderson, 2014/04/17
- [Qemu-devel] [PATCH 36/40] target-alpha: Use extract to get insn fields, Richard Henderson, 2014/04/17