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[Qemu-devel] [PULL 04/14] tci: Mask shift counts to avoid undefined beha
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 04/14] tci: Mask shift counts to avoid undefined behavior |
Date: |
Tue, 22 Apr 2014 14:05:54 -0700 |
TCG now requires unspecified behavior rather than a potential crash,
bring the C shift within the letter of the law.
Signed-off-by: Richard Henderson <address@hidden>
---
tci.c | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/tci.c b/tci.c
index 0202ed9..6523ab8 100644
--- a/tci.c
+++ b/tci.c
@@ -669,32 +669,32 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t
*tb_ptr)
t0 = *tb_ptr++;
t1 = tci_read_ri32(&tb_ptr);
t2 = tci_read_ri32(&tb_ptr);
- tci_write_reg32(t0, t1 << t2);
+ tci_write_reg32(t0, t1 << (t2 & 31));
break;
case INDEX_op_shr_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(&tb_ptr);
t2 = tci_read_ri32(&tb_ptr);
- tci_write_reg32(t0, t1 >> t2);
+ tci_write_reg32(t0, t1 >> (t2 & 31));
break;
case INDEX_op_sar_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(&tb_ptr);
t2 = tci_read_ri32(&tb_ptr);
- tci_write_reg32(t0, ((int32_t)t1 >> t2));
+ tci_write_reg32(t0, ((int32_t)t1 >> (t2 & 31)));
break;
#if TCG_TARGET_HAS_rot_i32
case INDEX_op_rotl_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(&tb_ptr);
t2 = tci_read_ri32(&tb_ptr);
- tci_write_reg32(t0, rol32(t1, t2));
+ tci_write_reg32(t0, rol32(t1, t2 & 31));
break;
case INDEX_op_rotr_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(&tb_ptr);
t2 = tci_read_ri32(&tb_ptr);
- tci_write_reg32(t0, ror32(t1, t2));
+ tci_write_reg32(t0, ror32(t1, t2 & 31));
break;
#endif
#if TCG_TARGET_HAS_deposit_i32
@@ -936,32 +936,32 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t
*tb_ptr)
t0 = *tb_ptr++;
t1 = tci_read_ri64(&tb_ptr);
t2 = tci_read_ri64(&tb_ptr);
- tci_write_reg64(t0, t1 << t2);
+ tci_write_reg64(t0, t1 << (t2 & 63));
break;
case INDEX_op_shr_i64:
t0 = *tb_ptr++;
t1 = tci_read_ri64(&tb_ptr);
t2 = tci_read_ri64(&tb_ptr);
- tci_write_reg64(t0, t1 >> t2);
+ tci_write_reg64(t0, t1 >> (t2 & 63));
break;
case INDEX_op_sar_i64:
t0 = *tb_ptr++;
t1 = tci_read_ri64(&tb_ptr);
t2 = tci_read_ri64(&tb_ptr);
- tci_write_reg64(t0, ((int64_t)t1 >> t2));
+ tci_write_reg64(t0, ((int64_t)t1 >> (t2 & 63)));
break;
#if TCG_TARGET_HAS_rot_i64
case INDEX_op_rotl_i64:
t0 = *tb_ptr++;
t1 = tci_read_ri64(&tb_ptr);
t2 = tci_read_ri64(&tb_ptr);
- tci_write_reg64(t0, rol64(t1, t2));
+ tci_write_reg64(t0, rol64(t1, t2 & 63));
break;
case INDEX_op_rotr_i64:
t0 = *tb_ptr++;
t1 = tci_read_ri64(&tb_ptr);
t2 = tci_read_ri64(&tb_ptr);
- tci_write_reg64(t0, ror64(t1, t2));
+ tci_write_reg64(t0, ror64(t1, t2 & 63));
break;
#endif
#if TCG_TARGET_HAS_deposit_i64
--
1.9.0
- [Qemu-devel] [PULL 00/14] tcg generic queue, Richard Henderson, 2014/04/22
- [Qemu-devel] [PULL 01/14] tcg: Fix warning (1 bit signed bitfield entry) and replace int by bool, Richard Henderson, 2014/04/22
- [Qemu-devel] [PULL 02/14] tcg: Use "unspecified behavior" for shifts, Richard Henderson, 2014/04/22
- [Qemu-devel] [PULL 03/14] tcg: Mask shift quantities while folding, Richard Henderson, 2014/04/22
- [Qemu-devel] [PULL 04/14] tci: Mask shift counts to avoid undefined behavior,
Richard Henderson <=
- [Qemu-devel] [PULL 06/14] tcg: Add TCGType parameter to tcg_target_const_match, Richard Henderson, 2014/04/22
- [Qemu-devel] [PULL 05/14] tcg: Fix out of range shift in deposit optimizations, Richard Henderson, 2014/04/22
- [Qemu-devel] [PULL 07/14] tcg-aarch64: Remove w constraint, Richard Henderson, 2014/04/22
- [Qemu-devel] [PULL 08/14] tcg-ppc64: Use the type parameter to tcg_target_const_match, Richard Henderson, 2014/04/22
- [Qemu-devel] [PULL 09/14] tcg-sparc: Use the type parameter to tcg_target_const_match, Richard Henderson, 2014/04/22
- [Qemu-devel] [PULL 10/14] tcg-s390: Remove W constraint, Richard Henderson, 2014/04/22
- [Qemu-devel] [PULL 12/14] tcg: Use tcg_gen_mulu2_i32 in tcg_gen_muls2_i32, Richard Henderson, 2014/04/22
- [Qemu-devel] [PULL 11/14] tcg: Relax requirement for mulu2_i32 on 32-bit hosts, Richard Henderson, 2014/04/22
- [Qemu-devel] [PULL 13/14] tcg: Fix fallback from muls2_i64 to mulu2_i64, Richard Henderson, 2014/04/22