[Qemu-devel] [PATCH v1 08/22] target-arm: A64: Add ELR entries for EL2 and 3

[Edgar E. Iglesias]

From: "Edgar E. Iglesias" <address@hidden>

Signed-off-by: Edgar E. Iglesias <address@hidden>
---
 target-arm/cpu.h     | 2 +-
 target-arm/machine.c | 8 ++++----
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 7bac416..fd8ce70 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -163,7 +163,7 @@ typedef struct CPUARMState {
     uint64_t daif; /* exception masks, in the bits they are in in PSTATE */
 
 #define ELR_EL_IDX(x) (x - 1)
-    uint64_t elr_el[1]; /* AArch64 exception link regs  */
+    uint64_t elr_el[3]; /* AArch64 exception link regs  */
     uint64_t sp_el[4]; /* AArch64 banked stack pointers */
 
     /* System control coprocessor (cp15) */
diff --git a/target-arm/machine.c b/target-arm/machine.c
index 6a87ef6..92ac621 100644
--- a/target-arm/machine.c
+++ b/target-arm/machine.c
@@ -222,9 +222,9 @@ static int cpu_post_load(void *opaque, int version_id)
 
 const VMStateDescription vmstate_arm_cpu = {
     .name = "cpu",
-    .version_id = 18,
-    .minimum_version_id = 18,
-    .minimum_version_id_old = 18,
+    .version_id = 19,
+    .minimum_version_id = 19,
+    .minimum_version_id_old = 19,
     .pre_save = cpu_pre_save,
     .post_load = cpu_post_load,
     .fields = (VMStateField[]) {
@@ -243,7 +243,7 @@ const VMStateDescription vmstate_arm_cpu = {
         VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 6),
         VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5),
         VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5),
-        VMSTATE_UINT64(env.elr_el[ELR_EL_IDX(1)], ARMCPU),
+        VMSTATE_UINT64_ARRAY(env.elr_el, ARMCPU, 3),
         VMSTATE_UINT64_ARRAY(env.sp_el, ARMCPU, 4),
         /* The length-check must come before the arrays to avoid
          * incoming data possibly overflowing the array.
-- 
1.8.3.2