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Re: [Qemu-devel] [PATCH v2 3/8] target-i386: fix set of registers zeroed
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From: |
Andreas Färber |
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Subject: |
Re: [Qemu-devel] [PATCH v2 3/8] target-i386: fix set of registers zeroed on reset |
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Date: |
Mon, 12 May 2014 09:56:21 +0200 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 |
Am 02.05.2014 16:33, schrieb Paolo Bonzini:
> BND0-3, BNDCFGU, BNDCFGS, BNDSTATUS were not zeroed on reset, but they
> should be (Intel Instruction Set Extensions Programming Reference
> 319433-015, pages 9-4 and 9-6). Same for YMM.
>
> XCR0 should be reset to 1.
>
> TSC and TSC_RESET were zeroed already by the memset, remove the explicit
> assignments.
>
> Cc: Andreas Färber <address@hidden>
> Signed-off-by: Paolo Bonzini <address@hidden>
Reviewed-by: Andreas Färber <address@hidden>
In general I'm happy if trivial target-specific tweaks like this can go
through someone else's tree. :)
Andreas
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- [Qemu-devel] [PATCH v2 0/8] x86: correctly implement soft reset, Paolo Bonzini, 2014/05/02
- [Qemu-devel] [PATCH v2 1/8] kvm: reset state from the CPU's reset method, Paolo Bonzini, 2014/05/02
- [Qemu-devel] [PATCH v2 3/8] target-i386: fix set of registers zeroed on reset, Paolo Bonzini, 2014/05/02
- Re: [Qemu-devel] [PATCH v2 3/8] target-i386: fix set of registers zeroed on reset,
Andreas Färber <=
- [Qemu-devel] [PATCH v2 4/8] target-i386: preserve FPU and MSR state on INIT, Paolo Bonzini, 2014/05/02
- [Qemu-devel] [PATCH v2 5/8] apic: do not accept SIPI on the bootstrap processor, Paolo Bonzini, 2014/05/02
- [Qemu-devel] [PATCH v2 2/8] kvm: forward INIT signals coming from the chipset, Paolo Bonzini, 2014/05/02
- [Qemu-devel] [PATCH v2 7/8] pc: port 92 reset requires a low->high transition, Paolo Bonzini, 2014/05/02
- [Qemu-devel] [PATCH v2 6/8] cpu: make CPU_INTERRUPT_RESET available on all targets, Paolo Bonzini, 2014/05/02