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[Qemu-devel] [PULL 06/15] target-i386: set eflags and cr0 prior to calli
From: |
Paolo Bonzini |
Subject: |
[Qemu-devel] [PULL 06/15] target-i386: set eflags and cr0 prior to calling cpu_x86_load_seg_cache() in smm_helper.c |
Date: |
Tue, 13 May 2014 14:57:15 +0200 |
From: Kevin O'Connor <address@hidden>
The cpu_x86_load_seg_cache() function inspects cr0 and eflags, so make
sure all changes to eflags and cr0 are done prior to loading the
segment caches.
Signed-off-by: Kevin O'Connor <address@hidden>
Signed-off-by: Paolo Bonzini <address@hidden>
---
target-i386/smm_helper.c | 34 +++++++++++++++++-----------------
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/target-i386/smm_helper.c b/target-i386/smm_helper.c
index 35901c9..4841d53 100644
--- a/target-i386/smm_helper.c
+++ b/target-i386/smm_helper.c
@@ -163,6 +163,13 @@ void do_smm_enter(X86CPU *cpu)
cpu_load_eflags(env, 0, ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C |
DF_MASK));
env->eip = 0x00008000;
+ cpu_x86_update_cr0(env,
+ env->cr[0] & ~(CR0_PE_MASK | CR0_EM_MASK | CR0_TS_MASK |
+ CR0_PG_MASK));
+ cpu_x86_update_cr4(env, 0);
+ env->dr[7] = 0x00000400;
+ CC_OP = CC_OP_EFLAGS;
+
cpu_x86_load_seg_cache(env, R_CS, (env->smbase >> 4) & 0xffff, env->smbase,
0xffffffff, 0);
cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffffffff, 0);
@@ -170,13 +177,6 @@ void do_smm_enter(X86CPU *cpu)
cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffffffff, 0);
cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffffffff, 0);
cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffffffff, 0);
-
- cpu_x86_update_cr0(env,
- env->cr[0] & ~(CR0_PE_MASK | CR0_EM_MASK | CR0_TS_MASK |
- CR0_PG_MASK));
- cpu_x86_update_cr4(env, 0);
- env->dr[7] = 0x00000400;
- CC_OP = CC_OP_EFLAGS;
}
void helper_rsm(CPUX86State *env)
@@ -191,16 +191,6 @@ void helper_rsm(CPUX86State *env)
#ifdef TARGET_X86_64
cpu_load_efer(env, ldq_phys(cs->as, sm_state + 0x7ed0));
- for (i = 0; i < 6; i++) {
- offset = 0x7e00 + i * 16;
- cpu_x86_load_seg_cache(env, i,
- lduw_phys(cs->as, sm_state + offset),
- ldq_phys(cs->as, sm_state + offset + 8),
- ldl_phys(cs->as, sm_state + offset + 4),
- (lduw_phys(cs->as, sm_state + offset + 2) &
- 0xf0ff) << 8);
- }
-
env->gdt.base = ldq_phys(cs->as, sm_state + 0x7e68);
env->gdt.limit = ldl_phys(cs->as, sm_state + 0x7e64);
@@ -238,6 +228,16 @@ void helper_rsm(CPUX86State *env)
cpu_x86_update_cr3(env, ldl_phys(cs->as, sm_state + 0x7f50));
cpu_x86_update_cr0(env, ldl_phys(cs->as, sm_state + 0x7f58));
+ for (i = 0; i < 6; i++) {
+ offset = 0x7e00 + i * 16;
+ cpu_x86_load_seg_cache(env, i,
+ lduw_phys(cs->as, sm_state + offset),
+ ldq_phys(cs->as, sm_state + offset + 8),
+ ldl_phys(cs->as, sm_state + offset + 4),
+ (lduw_phys(cs->as, sm_state + offset + 2) &
+ 0xf0ff) << 8);
+ }
+
val = ldl_phys(cs->as, sm_state + 0x7efc); /* revision ID */
if (val & 0x20000) {
env->smbase = ldl_phys(cs->as, sm_state + 0x7f00) & ~0x7fff;
--
1.8.3.1
- [Qemu-devel] [PULL 00/15] KVM patches for 2014-05-13, Paolo Bonzini, 2014/05/13
- [Qemu-devel] [PULL 01/15] target-i386: Remove unused data from local array, Paolo Bonzini, 2014/05/13
- [Qemu-devel] [PULL 02/15] kvm: make one_reg helpers available for everyone, Paolo Bonzini, 2014/05/13
- [Qemu-devel] [PULL 03/15] pci-assign: Fix a bug when map MSI-X table memory failed, Paolo Bonzini, 2014/05/13
- [Qemu-devel] [PULL 04/15] pci-assign: limit # of msix vectors, Paolo Bonzini, 2014/05/13
- [Qemu-devel] [PULL 05/15] target-i386: set eflags prior to calling svm_load_seg_cache() in svm_helper.c, Paolo Bonzini, 2014/05/13
- [Qemu-devel] [PULL 06/15] target-i386: set eflags and cr0 prior to calling cpu_x86_load_seg_cache() in smm_helper.c,
Paolo Bonzini <=
- [Qemu-devel] [PULL 07/15] target-i386: set eflags prior to calling cpu_x86_load_seg_cache() in seg_helper.c, Paolo Bonzini, 2014/05/13
- [Qemu-devel] [PULL 08/15] target-i386: the x86 CPL is stored in CS.selector - auto update hflags accordingly., Paolo Bonzini, 2014/05/13
- [Qemu-devel] [PULL 11/15] target-i386: fix set of registers zeroed on reset, Paolo Bonzini, 2014/05/13
- [Qemu-devel] [PULL 12/15] target-i386: preserve FPU and MSR state on INIT, Paolo Bonzini, 2014/05/13
- [Qemu-devel] [PULL 09/15] kvm: reset state from the CPU's reset method, Paolo Bonzini, 2014/05/13
- [Qemu-devel] [PULL 13/15] apic: do not accept SIPI on the bootstrap processor, Paolo Bonzini, 2014/05/13
- [Qemu-devel] [PULL 10/15] kvm: forward INIT signals coming from the chipset, Paolo Bonzini, 2014/05/13
- [Qemu-devel] [PULL 14/15] cpu: make CPU_INTERRUPT_RESET available on all targets, Paolo Bonzini, 2014/05/13
- [Qemu-devel] [PULL 15/15] pc: port 92 reset requires a low->high transition, Paolo Bonzini, 2014/05/13
- Re: [Qemu-devel] [PULL 00/15] KVM patches for 2014-05-13, Peter Maydell, 2014/05/15